7,150 research outputs found

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

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    © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

    Architectures for RF Frequency synthesizers

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    Frequency synthesizers are an essential building block of RF communication products. They can be found in traditional consumer products, in personal communication systems, and in optical communication equipment. Since frequency synthesizers are used in many different applications, different performance aspects may need to be considered in each case. The main body of the text describes a conceptual framework for analyzing the performance of PLL frequency synthesizers, and presents optimization procedures for the different performance aspects. The analysis of the PLL properties is performed with the use of the open-loop bandwidth and phase margin concepts, to enable the influence of higher-order poles to be taken into account from the beginning of the design process. The theoretical system analysis is complemented by descriptions of innovative system and building block architectures, by circuit implementations in bipolar and CMOS technologies, and by measurement results. Architectures for RF Frequency Synthesizers contains basic information for the beginner as well as in-depth knowledge for the experienced designer. It is widely illustrated with practical design examples used in industrial products.\ud Written for:\ud Electrical and electronic engineer

    The PreAmplifier ShAper for the ALICE TPC-Detector

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    In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber (TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an ASIC that integrates 16 identical channels, each consisting of Charge Sensitive Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network, two second-order bridged-T filters, two non-inverting level shifters and a start-up circuit. The circuit is optimized for a detector capacitance of 18-25 pF. For an input capacitance of 25 pF, the PASA features a conversion gain of 12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of 11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit recovers smoothly to the baseline in about 600 ns. An integral non-linearity of 0.19% with an output swing of about 2.1 V is also achieved. The total area of the chip is 18 mm2^2 and is implemented in AMS's C35B3C1 0.35 micron CMOS technology. Detailed characterization test were performed on about 48000 PASA circuits before mounting them on the ALICE TPC front-end cards. After more than two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA has demonstrated to fulfill all requirements

    A fully integrated multiband frequency synthesizer for WLAN and WiMAX applications

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    This paper presents a fractional N frequency synthesizer which covers WLAN and WiMAX frequencies on a single chip. The synthesizer is fully integrated in 0.35μm BiCMOS AMS technology except crystal oscillator. The synthesizer operates at four frequency bands (3.101-3.352GHz, 3.379-3.727GHz, 3.7-4.2GHz, 4.5-5.321GHz) to provide the specifications of 802.16 and 802.11 a/b/g/y. A single on-chip LC - Gm based VCO is implemented as the core of this synthesizer. Different frequency bands are selected via capacitance switching and fine tuning is done using varactor for each of these bands. A bandgap reference circuit is implemented inside of this charge pump block to generate temperature and power supply independent reference currents. Simulated settling time is around 10μsec. Total power consumption is measured to be 118.6mW without pad driving output buffers from a 3.3V supply. The phase noise of the oscillator is lower than -116.4dbc/Hz for all bands. The circuit occupies 2.784 mm2 on Si substrate, including DC, Digital and RF pads

    A Robust 43-GHz VCO in CMOS for OC-768 SONET Applications

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    In this paper, we present a 43-GHz LC-VCO in 0.13-/spl mu/m CMOS for use in SONET OC-768 optical networks. A tuned output buffer is used to provide 1.3 V/sub p-p/ (single-ended) into a 90-fF capacitive load as is required when the VCO is used in typical clock and data recovery (CDR) circuits. Phase noise is -90 dBc/Hz at a 1-MHz offset from the carrier; this meets SONET jitter specifications. The design has a tune range of 4.2%. The VCO, including output buffers, consumes 14 mA from a 1-V supply and occupies 0.06 mm/sup 2/ of die area. Modern CMOS process characteristics and the high center frequency of this design mean that the tank loss is not dominated by the integrated inductor, but rather by the tank capacitance. An area-efficient inductor design that does not require any optimization is used

    Experimental characterization of CMOS photonic devices

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    Current electrical interconnects in super-computers and high-performance processors present a bottleneck in terms of bandwidth and power consumption. A migration to the optical domain in order to cope with the connectivity between units (e.g. CPUs and memory) is needed to overcome these issues. Zero-change CMOS photonic devices represent a very attractive solution to the design of optical on-chip links. This approach makes use of up-to-date CMOS process, having enormous benefits regarding integration with state-of-the-art electronics. Designing and characterizing zero-change CMOS photonic devices is key for the future of optical interconnects. This thesis presents the characterization both theoretical and experimental of a Silicon-Germanium ring resonator modulator. It represents the first ever depletion modulator up to the date using SiGe as an active material. Moreover, it shows the best wavelength shift reported so far for zero-change CMOS modulators, enhancing the shift of a pure Silicon device. The demonstration of this device begins a new era of optical modulator designs using silicon-germanium to enhance modulation efficiency, and therefore reduce power consumption.Las interconexiones eléctricas de supercomputadores y de microprocesadores de alto rendimiento representan actualmente un bottleneck en cuanto a ancho de banda y potencia consumida se refiere. Se necesita una migración hacia el dominio óptico, para realizar la conectividad entre las diferentes unidades (por ejemplo CPU y memoria), con tal de superar estas limitaciones. Los dispositivos fabricados con la tecnología zero-change CMOS representan una solución muy atractiva para el diseño de links ópticos dentro de un chip. Esta técnica utiliza procesos CMOS actuales, beneficiándose así enormemente de la fácil integración con dispositivos electrónicos actuales. Diseñar y caracterizar dispositivos trabajando con zero-change CMOS es clave para el futuro de las interconexiones ópticas. Esta tesis presenta la caracterización tanto teórica como experimental de un modulador tipo ring resonator de Silicon-Germanium. Es el primer modulador de depletion utilizando SiGe como un material activo. Además, este dispositivo muestra el desplazamiento en longitud de onda más grande publicado hasta la fecha, comparándolo con otros moduladores zero-change CMOS, mejorando el desplazamiento de dispositivos de puro silicio. La demostración de este dispositivo comienza una nueva era de diseños de moduladores ópticos que utilizaran silicon-germanium para mejorar la eficiencia de modulación, y por lo tanto reducir el consumo de potencia.Les interconnexions elèctriques de super-computadors i microprocessadors de alt rendiment representen actualment un coll d'ampolla en quant a ample de banda i potència consumida. Es necessita una migració cap al domini òptic, per realitzar la connectivitat entre les diferents unitats (per exemple entre la CPU i la memòria), per tal de superar aquests problemes. Els dispositius fabricats sota zero-change CMOS technology representen una solució molt atractiva al disseny de links òptics dins d'un xip. Aquesta tècnica utilitza processos CMOS actuals, tenint enormes beneficis en quant a la integració amb dispositius electrònics actuals. Dissenyar i caracteritzar dispositius treballant amb zero-change CMOS és clau pel futur de les interconnexions òptiques del futur. Aquesta tesi presenta la caracterització tant teòrica com experimental d'un modulador ring resonator de Silicon-Germanium. Representa el primer modulador de depletion usant SiGe con un material actiu. A més a més, aquest dispositiu mostra el desplaçament en longitud d'ona més gran publicat fins ara en qualsevol dispositiu zero-change CMOS, millorant el desplaçament de dispositius de pur silici. La demostració d'aquest dispositiu comença una nova era de dissenys de moduladors òptics que utilitzaran silicon-germanium per millorar l'eficiència de modulació i per tant per reduir el consum de potència

    A Low Noise Sub-Sampling PLL in Which Divider Noise Is Eliminated and PD-CP Noise Is not multiplied by N^2

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    This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP)that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by N2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18- m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 X 0.45 m

    A mixed-signal integrated circuit for FM-DCSK modulation

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    This paper presents a mixed-signal application-specific integrated circuit (ASIC) for a frequency-modulated differential chaos shift keying (FM-DCSK) communication system. The chip is conceived to serve as an experimental platform for the evaluation of the FM-DCSK modulation scheme, and includes several programming features toward this goal. The operation of the ASIC is herein illustrated for a data rate of 500 kb/s and a transmission bandwidth in the range of 17 MHz. Using signals acquired from the test platform, bit error rate (BER) estimations of the overall FM-DCSK communication link have been obtained assuming wireless transmission at the 2.4-GHz ISM band. Under all tested propagation conditions, including multipath effects, the system obtains a BER = 10-3 for Eb/No lower than 28 dB.Ministerio de Ciencia y Tecnología TIC2003-0235
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