A fast engineering approach to high efficiency power amplifier linearization for avionics applications

This PhD thesis provides a fast engineering approach to the design of digital predistortion (DPD) linearizers from several perspectives: i) enhancing the off-line training performance of open-loop DPD, ii) providing robustness and reducing the computational complexity of the parameters identification subsystem and, iii) importing machine learning techniques to favor the automatic tuning of power amplifiers (PAs) and DPD linearizers with several free-parameters to maximize power efficiency while meeting the linearity specifications. One of the essential parts of unmanned aerial vehicles (UAV) is the avionics, being the radio control one of the earliest avionics present in the UAV. Unlike the control signal, for transferring user data (such as images, video, etc.) real-time from the drone to the ground station, large transmission rates are required. The PA is a key element in the transmitter chain to guarantee the data transmission (video, photo, etc.) over a long range from the ground station. The more linear output power, the better the coverage or alternatively, with the same coverage, better SNR allows the use of high-order modulation schemes and thus higher transmission rates are achieved. In the context of UAV wireless communications, the power consumption, size and weight of the payload is of significant importance. Therefore, the PA design has to take into account the compromise among bandwidth, output power, linearity and power efficiency (very critical in battery-supplied devices). The PA can be designed to maximize its power efficiency or its linearity, but not both. Therefore, a way to deal with this inherent trade-off is to design high efficient amplification topologies and let the PA linearizers take care of the linearity requirements. Among the linearizers, DPD linearization is the preferred solution to both academia and industry, for its high flexibility and linearization performance. In order to save as many computational and power resources as possible, the implementation of an open-loop DPD results a very attractive solution for UAV applications. This thesis contributes to the PA linearization, especially on off-line training for open-loop DPD, by presenting two different methods for reducing the design and operating costs of an open-loop DPD, based on the analysis of the DPD function. The first method focuses on the input domain analysis, proposing mesh-selecting (MeS) methods to accurately select the proper samples for a computationally efficient DPD parameter estimation. Focusing in the MeS method with better performance, the memory I-Q MeS method is combined with feature extraction dimensionality reduction technique to allow a computational complexity reduction in the identification subsystem by a factor of 65, in comparison to using the classical QR-LS solver and consecutive samples selection. In addition, the memory I-Q MeS method has been proved to be of crucial interest when training artificial neural networks (ANN) for DPD purposes, by significantly reducing the ANN training time. The second method involves the use of machine learning techniques in the DPD design procedure to enlarge the capacity of the DPD algorithm when considering a high number of free parameters to tune. On the one hand, the adaLIPO global optimization algorithm is used to find the best parameter configuration of a generalized memory polynomial behavioral model for DPD. On the other hand, a methodology to conduct a global optimization search is proposed to find the optimum values of a set of key circuit and system level parameters, that properly combined with DPD linearization and crest factor reduction techniques, can exploit at best dual-input PAs in terms of maximizing power efficiency along wide bandwidths while being compliant with the linearity specifications. The advantages of these proposed techniques have been validated through experimental tests and the obtained results are analyzed and discussed along this thesis.Aquesta tesi doctoral proporciona unes pautes per al disseny de linealitzadors basats en predistorsió digital (DPD) des de diverses perspectives: i) millorar el rendiment del DPD en llaç obert, ii) proporcionar robustesa i reduir la complexitat computacional del subsistema d'identificació de paràmetres i, iii) incorporació de tècniques d'aprenentatge automàtic per afavorir l'auto-ajustament d'amplificadors de potència (PAs) i linealitzadors DPD amb diversos graus de llibertat per poder maximitzar l’eficiència energètica i al mateix temps acomplir amb les especificacions de linealitat. Una de les parts essencials dels vehicles aeris no tripulats (UAV) _es l’aviònica, sent el radiocontrol un dels primers sistemes presents als UAV. Per transferir dades d'usuari (com ara imatges, vídeo, etc.) en temps real des del dron a l’estació terrestre, es requereixen taxes de transmissió grans. El PA _es un element clau de la cadena del transmissor per poder garantir la transmissió de dades a grans distàncies de l’estació terrestre. A major potència de sortida, més cobertura o, alternativament, amb la mateixa cobertura, millor relació senyal-soroll (SNR) la qual cosa permet l’ús d'esquemes de modulació d'ordres superiors i, per tant, aconseguir velocitats de transmissió més altes. En el context de les comunicacions sense fils en UAVs, el consum de potència, la mida i el pes de la càrrega útil són de vital importància. Per tant, el disseny del PA ha de tenir en compte el compromís entre ample de banda, potència de sortida, linealitat i eficiència energètica (molt crític en dispositius alimentats amb bateries). El PA es pot dissenyar per maximitzar la seva eficiència energètica o la seva linealitat, però no totes dues. Per tant, per afrontar aquest compromís s'utilitzen topologies amplificadores d'alta eficiència i es deixa que el linealitzador s'encarregui de garantir els nivells necessaris de linealitat. Entre els linealitzadors, la linealització DPD és la solució preferida tant per al món acadèmic com per a la indústria, per la seva alta flexibilitat i rendiment. Per tal d'estalviar tant recursos computacionals com consum de potència, la implementació d'un DPD en lla_c obert resulta una solució molt atractiva per a les aplicacions UAV. Aquesta tesi contribueix a la linealització del PA, especialment a l'entrenament fora de línia de linealitzadors DPD en llaç obert, presentant dos mètodes diferents per reduir el cost computacional i augmentar la fiabilitat dels DPDs en llaç obert. El primer mètode se centra en l’anàlisi de l’estadística del senyal d'entrada, proposant mètodes de selecció de malla (MeS) per seleccionar les mostres més significatives per a una estimació computacionalment eficient dels paràmetres del DPD. El mètode proposat IQ MeS amb memòria es pot combinar amb tècniques de reducció del model del DPD i d'aquesta manera poder aconseguir una reducció de la complexitat computacional en el subsistema d’identificació per un factor de 65, en comparació amb l’ús de l'algoritme clàssic QR-LS i selecció de mostres d'entrenament consecutives. El segon mètode consisteix en l’ús de tècniques d'aprenentatge automàtic pel disseny del DPD quan es considera un gran nombre de graus de llibertat (paràmetres) per sintonitzar. D'una banda, l'algorisme d’optimització global adaLIPO s'utilitza per trobar la millor configuració de paràmetres d'un model polinomial amb memòria generalitzat per a DPD. D'altra banda, es proposa una estratègia per l’optimització global d'un conjunt de paràmetres clau per al disseny a nivell de circuit i sistema, que combinats amb linealització DPD i les tècniques de reducció del factor de cresta, poden maximitzar l’eficiència de PAs d'entrada dual de gran ample de banda, alhora que compleixen les especificacions de linealitat. Els avantatges d'aquestes tècniques proposades s'han validat mitjançant proves experimentals i els resultats obtinguts s'analitzen i es discuteixen al llarg d'aquesta tesi

A 39GHz Balanced Power Amplifier with Enhanced Linearity in 45 nm SOI CMOS

With the high data rate communication systems that come with fifth-generation (5G) mobile networks, the shift of operation to millimeter-wave frequency becomes inevitable. The expected data rate in 5G is significantly improved over 4G by utilizing the large available channel bandwidth at millimeter wave frequencies and complex data modulation schemes. With this increase in operation frequency, many new challenges arise and research efforts are made to tackle them. Among them, the phased array system is one of the hottest topics as it can be made use of to improve the link budget and overcome the path loss challenge at these frequencies. As the last circuit component in the transmitter's front-end right before the antenna, the power amplifier (PA) is one of the most crucial components with significant effects on overall system performance. Many of the traditional challenges of CMOS PA design such as output power and efficiency, are now compounded with the additional challenges that are imposed on complementary metal-oxide semiconductor (CMOS) PAs in millimeter wave phased array systems. This thesis presents a balanced power amplifier design with enhanced linearity in GlobalFoundries' 45nm silicon-on-insulator (SOI) CMOS technology. By using the balanced topology with each stage terminating with a differential 2-stacked architecture, the PA achieves saturated output power of over 21 dBm. Each of the two identical sub-PAs in the balanced topology uses 2-stage topology with driver and PA co-design method. The linearity is enhanced through careful choice of biasing point and a strategic inter-stage matching network design methodology, resulting in amplitude-to-phase distortion below 1 degree up to the output 1dB compression level of over 19 dBm. The balanced amplifier topology significantly reduces the PA performance variation over mismatched load impedance at the output, thus improving the PA performance over different antenna active impedance caused by varying phased array beam-steering angles. In addition to this, the balanced topology also optimizes the PA input and output return loss, giving a better matching than -20 dB at both input and output, and minimizing the risk of potential issues and performance degradation in the system integration phase. Lastly, the compact transformer based matching networks and quadrature hybrids reduce the chip area occupation of this PA, resulting in a compact design with competitive performance

A Novel Power-Scalable Wideband Power Amplifier Linearization Technique

Global mobile traffic is expected to continue to increase at an astonishing rate in the future, due to the ever-increasing number of mobile phone subscribers and the adoption of smart devices which generate significantly more mobile traffic. To satisfy this growth in demand, it is envisioned that future 5th Generation (5G) mobile networks will utilize lower powered small-cell base stations and base stations with large antenna arrays to greatly improve network coverage and capacity. A power amplifier (PA) is a critical component in a base station’s transmitter, required to boost the signal power such that it is high enough for transmission to the intended receiver. The design of the PA for 5G base stations, however, presents new challenges to designers. When driven with modern wideband communication signals, the PA must be both efficient and linear in order to minimize power consumption, improve reliability, maintain transmission accuracy, and avoid interference with neighbouring signals. In conventional high-powered macrocell base station designs, the aforementioned requirements are usually satisfied using a two-step procedure. First, the PA is designed using a Doherty power amplifier (DPA) topology, which has high efficiency, but poor linearity. Then, digital predistortion (DPD) linearization techniques are applied to ensure that the DPA attains the required linearity performance. However, for the lower-powered PAs needed in small cells and large antenna arrays, the relatively high power overhead of DPD techniques, which does not scale down as the power range of the PA decreases, make them unattractive PA linearization solutions. In response, a new PA linearization technique is proposed and developed in this thesis. It is based on the design and addition of a linearization amplifier (LA), an approach which can help the PA attain the required linearity even when it is driven with modern communication signals with very wide bandwidths. Of particular note, the LA’s power consumption is relatively low, it scales with the PA’s power range, and it does not increase with signal bandwidth. These qualities make it highly suitable for use with PAs in future 5G small-cell base stations and base stations with large antenna arrays. To validate the proposed technique’s effectiveness, a prototype circuit was designed, fabricated and applied to a high peak efficiency 6 W class AB PA with a centre frequency of 850 MHz. When stimulated by a wideband 40 MHz signal, the PA’s adjacent channel leakage ratio (ACLR) was improved by up to 13 dB after the addition of the LA. This enabled the PA to achieve an ACLR of about -45 dBc without the use of any other linearization techniques. Significant ACLR improvements were also observed for signals with even wider bandwidths of up to 160 MHz. Moreover, it was shown that the LA could be used in conjunction with a simple predistorter to further improve the efficiency and linearity of the class AB PA. Next, the LA is augmented with a conventional DPA design to form a new linear DPA topology that was able to achieve a better linearity-efficiency trade-off compared to the linearized class AB PA. To accomplish this, a study of the interactions between the LA and DPA circuitries was conducted and a design strategy was developed to determine the circuit parameters that maximized ACLR improvement while minimizing power consumption. For validation purposes, this strategy was applied to design a proof-of-concept prototype with a centre frequency of 800 MHz and a peak envelope power of 12 W. With the addition of the LA, a more than 11 dB improvement of the ACLR was obtained at the prototype’s output when it was driven with signals with up to 40 MHz of modulation bandwidth: an ACLR of about -45 dBc or better was achieved over wide average power range. As expected, the efficiency of the linear DPA topology remained significantly higher than the linearized class AB PA for all signals tested. Another challenge faced in particular by PAs in a large antenna array, is that it will experience dynamic load impedance variations due to antenna coupling. This unwanted variation in the load impedance can cause instability and significant distortions at the output of the PA that is difficult to remedy using conventional techniques. To address these issues, it is shown in the last part of this thesis that the LA can be used to mitigate this problem by minimizing the amount of load impedance variation seen by the PA due to antenna coupling, such that it remains closer to its optimal value, and by maintaining excellent linearization across a wide range of load impedance values