Modeling, design and scheduling of computer integrated manufacturing and demanufacturing systems

This doctoral dissertation work aims to provide a discrete-event system-based methodology for design, implementation, and operation of flexible and agile manufacturing and demanufacturing systems. After a review of the current academic and industrial activities in these fields, a Virtual Production Lines (VPLs) design methodology is proposed to facilitate a Manufacturing Execution System integrated with a shop floor system. A case study on a back-end semiconductor line is performed to demonstrate that the proposed methodology is effective to increase system throughput and decrease tardiness. An adaptive algorithm is proposed to deal with the machine failure and maintenance. To minimize the environmental impacts caused by end-of-life or faulty products, this research addresses the fundamental design and implementation issues of an integrated flexible demanufacturing system (IFDS). In virtue of the success of the VPL design and differences between disassembly and assembly, a systematic approach is developed for disassembly line design. This thesis presents a novel disassembly planning and demanufacturing scheduling method for such a system. Case studies on the disassembly of personal computers are performed illustrating how the proposed approaches work

VLSI Revisited - Revival in Japan

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government - through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors, Hitachi, Sony, Toshiba, Elpida, Renesas, Sematech, VLSI, JESSI, MEDEA, ASPLA, MIRAI, innovation system

VLSI REVISITED – REVIVAL IN JAPAN

This paper describes the abundance of semiconductor consortia that have come into existence in Japan since the mid-1990s. They clearly reflect the ambition of the government – through its reorganized ministry METI and company initiatives - to regain some of the industrial and technological leadership that Japan has lost. The consortia landscape is very different in Japan compared with EU and the US. Outside Japan the universities play a much bigger and very important role. In Europe there has emerged close collaboration, among national government agencies, companies and the EU Commission in supporting the IT sector with considerable attention to semiconductor technologies. Another major difference, and possibly the most important one, is the fact that US and EU consortia include and mix partners from different areas of the semiconductor landscape including wafer makers, material suppliers, equipment producers and integrated device makers.semiconductors; Hitachi; Sony; Toshiba; Elpida; Renesas; Sematech; VLSI; JESSI; MEDEA; ASPLA; MIRAI; innovation system

Internationalisation of Innovation: Why Chip Design Moving to Asia

This paper will appear in International Journal of Innovation Management, special issue in honor of Keith Pavitt, (Peter Augsdoerfer, Jonathan Sapsed, and James Utterback, guest editors), forthcoming. Among Keith Pavitt's many contributions to the study of innovation is the proposition that physical proximity is advantageous for innovative activities that involve highly complex technological knowledge But chip design, a process that creates the greatest value in the electronics industry and that requires highly complex knowledge, is experiencing a massive dispersion to leading Asian electronics exporting countries. To explain why chip design is moving to Asia, the paper draws on interviews with 60 companies and 15 research institutions that are doing leading-edge chip design in Asia. I demonstrate that "pull" and "policy" factors explain what attracts design to particular locations. But to get to the root causes that shift the balance in favor of geographical decentralization, I examine "push" factors, i.e. changes in design methodology ("system-on-chip design") and organization ("vertical specialization" within global design networks). The resultant increase in knowledge mobility explains why chip design - that, in Pavitt's framework is not supposed to move - is moving from the traditional centers to a few new specialized design clusters in Asia. A completely revised and updated version has been published as: " Complexity and Internationalisation of Innovation: Why is Chip Design Moving to Asia?," in International Journal of Innovation Management, special issue in honour of Keith Pavitt, Vol. 9,1: 47-73.

The Economics of Electronics Industry: Competitive Dynamics and Industrial Organization

This entry highlights fundamental changes in the electronics industry that have transformed its competitive dynamics and industrial organization: a high and growing knowledge intensity; the rapid pace of change in technologies and markets; and extensive globalization. That explosive mixture of forces has created two inter-related puzzles. The first puzzle is that a high degree of globalization may well go hand in hand with high and increasing concentration. This runs counter to the dominant view, based on the assumption of neo-classical trade theory, that globalization will increase competition and hence will act as a powerful equalizer both among nations and among firms. Multinational corporations, after all, may not be such effective "spoilers of concentration", as claimed by Richard Caves (1982). The second related puzzle is that this industry fails to act like a stable global oligopoly, even when concentration is extremely high: a market positions are highly volatile, new entry is possible, and not even market leaders can count on a guaranteed survival.

Virtual metrology for plasma etch processes.

Plasma processes can present dicult control challenges due to time-varying dynamics and a lack of relevant and/or regular measurements. Virtual metrology (VM) is the use of mathematical models with accessible measurements from an operating process to estimate variables of interest. This thesis addresses the challenge of virtual metrology for plasma processes, with a particular focus on semiconductor plasma etch. Introductory material covering the essentials of plasma physics, plasma etching, plasma measurement techniques, and black-box modelling techniques is rst presented for readers not familiar with these subjects. A comprehensive literature review is then completed to detail the state of the art in modelling and VM research for plasma etch processes. To demonstrate the versatility of VM, a temperature monitoring system utilising a state-space model and Luenberger observer is designed for the variable specic impulse magnetoplasma rocket (VASIMR) engine, a plasma-based space propulsion system. The temperature monitoring system uses optical emission spectroscopy (OES) measurements from the VASIMR engine plasma to correct temperature estimates in the presence of modelling error and inaccurate initial conditions. Temperature estimates within 2% of the real values are achieved using this scheme. An extensive examination of the implementation of a wafer-to-wafer VM scheme to estimate plasma etch rate for an industrial plasma etch process is presented. The VM models estimate etch rate using measurements from the processing tool and a plasma impedance monitor (PIM). A selection of modelling techniques are considered for VM modelling, and Gaussian process regression (GPR) is applied for the rst time for VM of plasma etch rate. Models with global and local scope are compared, and modelling schemes that attempt to cater for the etch process dynamics are proposed. GPR-based windowed models produce the most accurate estimates, achieving mean absolute percentage errors (MAPEs) of approximately 1:15%. The consistency of the results presented suggests that this level of accuracy represents the best accuracy achievable for the plasma etch system at the current frequency of metrology. Finally, a real-time VM and model predictive control (MPC) scheme for control of plasma electron density in an industrial etch chamber is designed and tested. The VM scheme uses PIM measurements to estimate electron density in real time. A predictive functional control (PFC) scheme is implemented to cater for a time delay in the VM system. The controller achieves time constants of less than one second, no overshoot, and excellent disturbance rejection properties. The PFC scheme is further expanded by adapting the internal model in the controller in real time in response to changes in the process operating point

Virtual metrology for plasma etch processes.

Plasma processes can present dicult control challenges due to time-varying dynamics and a lack of relevant and/or regular measurements. Virtual metrology (VM) is the use of mathematical models with accessible measurements from an operating process to estimate variables of interest. This thesis addresses the challenge of virtual metrology for plasma processes, with a particular focus on semiconductor plasma etch. Introductory material covering the essentials of plasma physics, plasma etching, plasma measurement techniques, and black-box modelling techniques is rst presented for readers not familiar with these subjects. A comprehensive literature review is then completed to detail the state of the art in modelling and VM research for plasma etch processes. To demonstrate the versatility of VM, a temperature monitoring system utilising a state-space model and Luenberger observer is designed for the variable specic impulse magnetoplasma rocket (VASIMR) engine, a plasma-based space propulsion system. The temperature monitoring system uses optical emission spectroscopy (OES) measurements from the VASIMR engine plasma to correct temperature estimates in the presence of modelling error and inaccurate initial conditions. Temperature estimates within 2% of the real values are achieved using this scheme. An extensive examination of the implementation of a wafer-to-wafer VM scheme to estimate plasma etch rate for an industrial plasma etch process is presented. The VM models estimate etch rate using measurements from the processing tool and a plasma impedance monitor (PIM). A selection of modelling techniques are considered for VM modelling, and Gaussian process regression (GPR) is applied for the rst time for VM of plasma etch rate. Models with global and local scope are compared, and modelling schemes that attempt to cater for the etch process dynamics are proposed. GPR-based windowed models produce the most accurate estimates, achieving mean absolute percentage errors (MAPEs) of approximately 1:15%. The consistency of the results presented suggests that this level of accuracy represents the best accuracy achievable for the plasma etch system at the current frequency of metrology. Finally, a real-time VM and model predictive control (MPC) scheme for control of plasma electron density in an industrial etch chamber is designed and tested. The VM scheme uses PIM measurements to estimate electron density in real time. A predictive functional control (PFC) scheme is implemented to cater for a time delay in the VM system. The controller achieves time constants of less than one second, no overshoot, and excellent disturbance rejection properties. The PFC scheme is further expanded by adapting the internal model in the controller in real time in response to changes in the process operating point

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Concentric distributed active transformers (DAT) are used to implement a fully-integrated quad-band power amplifier (PA) in a standard 130 nm CMOS process. The DAT enables the power amplifier to integrate the input and output matching networks on the same silicon die. The PA integrates on-chip closed-loop power control and operates under supply voltages from 2.9 V to 5.5 V in a standard micro-lead-frame package. It shows no oscillations, degradation, or failures for over 2000 hours of operation with a supply of 6 V at 135° under a VSWR of 15:1 at all phase angles and has also been tested for more than 2 million device-hours (with ongoing reliability monitoring) without a single failure under nominal operation conditions. It produces up to +35 dBm of RF power with power-added efficiency of 51%