22 research outputs found
A review on reversible logic gates
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.
Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic
Design of Power-Efficient Structures of the CAM Cell using a New Approach in QCA Nanoelectronics Technology
Quantum-dot Cellular Automata (QCA) is a new emerging nano-electronic technology. Owing to its many fa-vorable features such as low energy requirements, high speed, and small size, QCA is being actively suggested as a future CMOS replacement by researchers. Many digital circuits have been introduced in QCA technology, most of them aiming to reach the function with optimum construction in terms of area, cell count and power consumption. The memory circuit is the main building block in the digital system therefore the researchers paid attention to design the memory cells with minimum requirements. In this paper, a new methodology is intro-duced to design two forms of CAM cell. The proposed designs required two 2:1 multiplexers, one OR gate and one inverter. The first proposed design reduces the power consumption by 53.3%, 35% and 25.9% at (0.5 Ek, 1 Ek, and 1.5 Ek) while the second design by 53.2%, 31.9% and 20.5% (0.5 Ek, 1 Ek, and 1.5 Ek) respectively
Novel Defect Terminolgy Beside Evaluation And Design Fault Tolerant Logic Gates In Quantum-Dot Cellular Automata
Quantum dot Cellular Automata (QCA) is one of the important nano-level technologies for implementation of both combinational and sequential systems. QCA have the potential to achieve low power dissipation and operate high speed at THZ frequencies. However large probability of occurrence fabrication defects in QCA, is a fundamental challenge to use this emerging technology. Because of these various defects, it is necessary to obtain exhaustive recognition about these defects. In this paper a complete survey of different QCA faults are presented first. Then some techniques to improve fault tolerance in QCA circuits explained. The effects of missing cell as an important fault on XOR gate that is one of important basic building block in QCA technology is then discussed by exhaustive simulations. Improvement technique is then applied to these XOR structures and then structures are resimulated to measure their fault tolerance improvement due to using these fault tolerance technique. The result show that different QCA XOR gates have different sensitivity against this fault. After using improvement technique, the tolerance of XOR gates have been increased, furthermore in terms of sensitivity against this defect XORs show similar behavior that indicate the effectiveness of improvement have been made
Performance analysis of fault-tolerant nanoelectronic memories
Performance growth in microelectronics, as described by Moore’s law, is steadily
approaching its limits. Nanoscale technologies are increasingly being explored as a
practical solution to sustaining and possibly surpassing current performance trends of
microelectronics. This work presents an in-depth analysis of the impact on performance,
of incorporating reliability schemes into the architecture of a crossbar molecular switch
nanomemory and demultiplexer. Nanoelectronics are currently in their early stages, and
so fabrication and design methodologies are still in the process of being studied and
developed. The building blocks of nanotechnology are fabricated using bottom-up
processes, which leave them highly susceptible to defects. Hence, it is very important that
defect and fault-tolerant schemes be incorporated into the design of nanotechnology
related devices.
In this dissertation, we focus on the study of a novel and promising class of
computer chip memories called crossbar molecular switch memories and their
demultiplexer addressing units. A major part of this work was the design of a defect and
fault tolerance scheme we called the Multi-Switch Junction (MSJ) scheme. The MSJ scheme takes advantage of the regular array geometry of the crossbar nanomemory to
create multiple switches in the fabric of the crossbar nanomemory for the storage of a
single bit.
Implementing defect and fault tolerant schemes come at a performance cost to the
crossbar nanomemory; the challenge becomes achieving a balance between device
reliability and performance. We have studied the reliability induced performance penalties
as they relate to the time (delay) it takes to access a bit, and the amount of power
dissipated by the process. Also, MSJ was compared to the banking and error correction
coding fault tolerant schemes. Studies were also conducted to ascertain the potential
benefits of integrating our MSJ scheme with the banking scheme. Trade-off analysis
between access time delay, power dissipation and reliability is outlined and presented in
this work.
Results show the MSJ scheme increases the reliability of the crossbar
nanomemory and demultiplexer. Simulation results also indicated that MSJ works very
well for smaller nanomemory array sizes, with reliabilities of 100% for molecular switch
failure rates in the 10% or less range
Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices
This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results
Quantum Computing and Communications
This book explains the concepts and basic mathematics of quantum computing and communication. Chapters cover such topics as quantum algorithms, photonic implementations of discrete-time quantum walks, how to build a quantum computer, and quantum key distribution and teleportation, among others