The effect of coefficient quantization optimization on filtering performance and gate count

Abstract. Digital filters are an essential component of Digital Signal Processing (DSP) applications and play a crucial role in removing unwanted signal components from a desired signal. However, digital filters are known to be resource-intensive and consume a large amount of power, making it important to optimize their design in order to minimize hardware requirements such as multipliers, adders, and registers. This trade-off between filter performance and hardware consumption can be influenced by the quantization of filter coefficients. Therefore, this thesis investigates the quantization of Finite Impulse Response (FIR) filter coefficients and analyzes its impact on filter performance and hardware resource consumption. A method called dynamic quantization is introduced and an algorithm for step-by-step dynamic quantization is provided to improve upon the results obtained with the classical fixed point quantization method. To demonstrate the effectiveness of this approach, the dynamic quantization of filter coefficients for a Low-pass Equiripple FIR filter is examined and a comparative study of the magnitude response and hardware consumption of the generated filter using both the classical and dynamic quantization methods is presented. By understanding the trade-offs and benefits of each quantization method, engineers can make informed decisions about the most appropriate approach for their specific application

Hardware implementation of daubechies wavelet transforms using folded AIQ mapping

The Discrete Wavelet Transform (DWT) is a popular tool in the field of image and video compression applications. Because of its multi-resolution representation capability, the DWT has been used effectively in applications such as transient signal analysis, computer vision, texture analysis, cell detection, and image compression. Daubechies wavelets are one of the popular transforms in the wavelet family. Daubechies filters provide excellent spatial and spectral locality-properties which make them useful in image compression. In this thesis, we present an efficient implementation of a shared hardware core to compute two 8-point Daubechies wavelet transforms. The architecture is based on a new two-level folded mapping technique, an improved version of the Algebraic Integer Quantization (AIQ). The scheme is developed on the factorization and decomposition of the transform coefficients that exploits the symmetrical and wrapping structure of the matrices. The proposed architecture is parallel, pipelined, and multiplexed. Compared to existing designs, the proposed scheme reduces significantly the hardware cost, critical path delay and power consumption with a higher throughput rate. Later, we have briefly presented a new mapping scheme to error-freely compute the Daubechies-8 tap wavelet transform, which is the next transform of Daubechies-6 in the Daubechies wavelet series. The multidimensional technique maps the irrational transformation basis coefficients with integers and results in considerable reduction in hardware and power consumption, and significant improvement in image reconstruction quality

Implementation of Area Efficient Multiple Passband FIR Filter for 5G Applications

971-978In television, mobile and digital signal processing applications, efficient multiband filters have great usage. The proposed architecture gives the Reconfigurable Finite Impulse Response (FIR) filter with multiple pass bands. Implementation of architecture utilizes FIR filter with control logic and frequency selection circuit. By adjusting the parameters of the filter, proper bandwidth of the pass band can be achieved and the ripple content in the pass band and stop band can be controlled. The efficient way to adjust the bandwidth is to choose the effective value of the filter length and coefficients. The area efficient multiple passband FIR filter using control logic has been proposed with order (n = 4 and 11). Target device that has been selected for implementation is Field Programmable Gate Array (FPGA) Virtex 4 Device. The Look-Up Tables (LUT) utilization for the implemented architecture with length of filter (n = 11) is observed to be 6%

Digital instrumentation for the measurement of high spectral purity signals

Improvements on electronic technology in recent years have allowed the application of digital techniques in time and frequency metrology where low noise and high accuracy are required, yielding flexibility in systems implementation and setup. This results in measurement systems with extended capabilities, additional functionalities and ease of use. The Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs), as the system front-end, set the ultimate performance of the system in terms of noise. The noise characterization of these components will allow performing punctual considerations on the study of the implementation feasibility of new techniques and for the selection of proper components according to the application requirements. Moreover, most commercial platforms based on FPGA are clocked by quartz oscillators whose accuracy and frequency stability are not suitable for many time and frequency applications. In this case, it is possible to take advantage of the internal Phase Locked Loop (PLL) for generating the internal clock from an external frequency reference. However, the PLL phase noise could degrade the oscillator stability thereby limiting the entire system performance becoming a critical component for digital instrumentation. The information available currently in literature, describes in depth the features of these devices at frequency offsets far from the carrier. However, the information close to the carrier is a more important concern for time and frequency applications. In this frame, my PhD work is focused on understanding the limitations of the critical blocks of digital instrumentation for time and frequency metrology. The aim is to characterize the noise introduced by these blocks and in this manner to be able to predict their effects on a specific application. This is done by modeling the noise introduced by each component and by describing them in terms of general and technical parameters. The parameters of the models are identified and extracted through the corresponding method proposed accordingly to the component operation. This work was validated by characterizing a commercially available platform, Red Pitaya. This platform is an open source embedded system whose resolution and speed (14 bit, 125 MSps) are reasonably close to the state of the art of ADCs and DACs (16 bit, 350 MSps or 14 bit, 1 GSps/3GSPs) and it is potentially sufficient for the implementation of a complete instrument. The characterization results lead to the noise limitations of the platform and give a guideline for instrumentation design techniques. Based on the results obtained from the noise characterization, the implementation of a digital instrument for frequency transfer using fiber link was performed on the Red Pitaya platform. In this project, a digital implementation for the detection and compensation of the phase noise induced by the fiber is proposed. The beat note, representing the fiber length variations, is acquired directly with a high speed ADC followed by a fully digital phase detector. Based on the characterization results, it was expected a limitation in the phase noise measurement given by the PLL. First measurements of this implementation were performed using the 150 km-long buried fibers, placed in the same cables between INRiM and the Laboratoire Souterrain de Modane (LSM) on the Italy-France border. The two fibers are joined together at LSM to obtain a 300 km loop with both ends at INRiM. From these results the noise introduced by the digital system was verified in agreement with characterization results. Further test and improvements will be performed for having a finished system which is intended to be used on the Italian Link for Frequency and Time from Turin to Florence that is 642-km long and to its extension in the rest of Italy that is foreseen in the next future. Currently, a higher performance platform is under assessment by applying the tools and concepts developed along the PhD. The purpose of this project is the implementation of a state of the art phasemeter whose architecture is based on the DAC. In order to estimate the ultimate performance of the instrument, the DAC characterization is under development and preliminary measurements are also reported here