On prefilters for digital FIR filter design

A new family of digital prefilter structures is introduced, based on the Dolph-Chebyshev function. These prefilters can be combined with appropriately designed "equalizer" filters based on equiripple methods, leading to efficient FIR digital filter designs. Design examples are included, demonstrating the simplicity of the resulting designs, as compared to conventional equiripple designs

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

Fir filter design for area efficient implementation /

In this dissertation, a variable precision algorithm based on sensitivity analysis is proposed for reducing the wordlength of the coefficients and/or the number of nonzero bits of the coefficients to reduce the complexity required in the implementation. Further space savings is possible if the proposed algorithm is associated with our optimal structures and derived scaling algorithm. We also propose a structure to synthesize FIR filters using the improved prefilter equalizer structure with arbitrary bandwidth, and our proposed filter structure reduces the area required. Our improved design is targeted at improving the prefilters based on interpolated FIR filter and frequency masking design and aims to provide a sharp transition-band as well as increasing the stopband attenuation. We use an equalizer designed to compensate the prefilter performance. In this dissertation, we propose a systematic procedure for designing FIR filters implementations. Our method yields a good design with low coefficient sensitivity and small order while satisfying design specifications. The resulting hardware implementation is suitable for use in custom hardware such as VLSI and Field Programmable Gate Arrays (FPGAs).FIR filters are preferred for many Digital Signal Processing applications as they have several advantages over IIR filters such as the possibility of exact linear phase, shorter required wordlength and guaranteed stability. However, FIR filter applications impose several challenges on the implementations of the systems, especially in demanding considerably more arithmetic operations and hardware components. This dissertation focuses on the design and implementation of FIR filters in hardware to reduce the space required without loss of performance

Adaptive interference suppression for DS-CDMA systems based on interpolated FIR filters with adaptive interpolators in multipath channels

In this work we propose an adaptive linear receiver structure based on interpolated finite impulse response (FIR) filters with adaptive interpolators for direct sequence code division multiple access (DS-CDMA) systems in multipath channels. The interpolated minimum mean-squared error (MMSE) and the interpolated constrained minimum variance (CMV) solutions are described for a novel scheme where the interpolator is rendered time-varying in order to mitigate multiple access interference (MAI) and multiple-path propagation effects. Based upon the interpolated MMSE and CMV solutions we present computationally efficient stochastic gradient (SG) and exponentially weighted recursive least squares type (RLS) algorithms for both receiver and interpolator filters in the supervised and blind modes of operation. A convergence analysis of the algorithms and a discussion of the convergence properties of the method are carried out for both modes of operation. Simulation experiments for a downlink scenario show that the proposed structures achieve a superior BER convergence and steady-state performance to previously reported reduced-rank receivers at lower complexity

Efficient design of a class of multiplier-less perfect reconstruction two-channel filter banks and wavelets with prescribed output accuracy

The 11th IEEE Signal Processing Workshop on Statistical Signal Processing, Singapore, 6-8 August 2001This paper proposes a novel algorithm for the design and hardware reduction of a class of multiplier-less two-channel PR filter banks (FBs) using sum-of-powers-of-two (SOPOT) coefficient. It minimizes a more realistic hardware cost, such as adder cells, subject to a prescribe output accuracy taking into account of the rounding and overflow effects, instead of using just the SOPOT terms as in conventional method. Furthermore, by implementing the filters in the FBs using multiplier-block (MB), significant overall saving in hardware resources can be achieved. An effective random search algorithm is also proposed to solve the design problem, which is also applicable to PR IIR FBs with highly nonlinear objective functions.published_or_final_versio

The effect of coefficient quantization optimization on filtering performance and gate count

Abstract. Digital filters are an essential component of Digital Signal Processing (DSP) applications and play a crucial role in removing unwanted signal components from a desired signal. However, digital filters are known to be resource-intensive and consume a large amount of power, making it important to optimize their design in order to minimize hardware requirements such as multipliers, adders, and registers. This trade-off between filter performance and hardware consumption can be influenced by the quantization of filter coefficients. Therefore, this thesis investigates the quantization of Finite Impulse Response (FIR) filter coefficients and analyzes its impact on filter performance and hardware resource consumption. A method called dynamic quantization is introduced and an algorithm for step-by-step dynamic quantization is provided to improve upon the results obtained with the classical fixed point quantization method. To demonstrate the effectiveness of this approach, the dynamic quantization of filter coefficients for a Low-pass Equiripple FIR filter is examined and a comparative study of the magnitude response and hardware consumption of the generated filter using both the classical and dynamic quantization methods is presented. By understanding the trade-offs and benefits of each quantization method, engineers can make informed decisions about the most appropriate approach for their specific application

Design and multiplier-less implementation of a class of two-channel PR FIR filterbanks and wavelets with low system delay

In this paper, a new method for designing two-channel PR FIR filterbanks with low system delay is proposed. It is based on the generalization of the structure previously proposed by Phoong et al. Such structurally PR filterbanks are parameterized by two functions (β(z) and α(z)) that can be chosen as linear-phase FIR or allpass functions to construct FIR/IIR filterbanks with good frequency characteristics. The case of using identical β(z) and α(z) was considered by Phoong et al. with the delay parameter M chosen as 2N - 1. In this paper, the more general case of using different nonlinear-phase FIR functions for β(z) and α(z) is studied. As the linear-phase constraint is relaxed, the lengths of β(z) and α(z) are no longer restricted by the delay parameters of the filterbanks. Hence, higher stopband attenuation can still be achieved at low system delay. The design of the proposed low-delay filterbanks is formulated as a complex polynomial approximation problem, which can be solved by the Remez exchange algorithm or analytic formula with very low complexity. In addition, the orders and delay parameters can be estimated from the given filter specifications using a simple empirical formula. Therefore, low-delay two-channel PR filterbanks with flexible stopband attenuation and cutoff frequencies can be designed using existing filter design algorithms. The generalization of the present approach to the design of a class of wavelet bases associated with these low-delay filterbanks and its multiplier-less implementation using the sum of powers-of-two coefficients are also studied.published_or_final_versio