348 research outputs found

    Cognitive Radio for Emergency Networks

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    In the scope of the Adaptive Ad-hoc Freeband (AAF) project, an emergency network built on top of Cognitive Radio is proposed to alleviate the spectrum shortage problem which is the major limitation for emergency networks. Cognitive Radio has been proposed as a promising technology to solve todayâ?~B??~D?s spectrum scarcity problem by allowing a secondary user in the non-used parts of the spectrum that aactully are assigned to primary services. Cognitive Radio has to work in different frequency bands and various wireless channels and supports multimedia services. A heterogenous reconfigurable System-on-Chip (SoC) architecture is proposed to enable the evolution from the traditional software defined radio to Cognitive Radio

    Reconfigurable architectures for beyond 3G wireless communication systems

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    Domain specific high performance reconfigurable architecture for a communication platform

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    The Chameleon Architecture for Streaming DSP Applications

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    We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm2^2 in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

    Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

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    Turbo codes are extensively used in current communications standards and have a promising outlook for future generations. The advantages of software defined radio, especially dynamic reconfiguration, make it very attractive in this multi-standard scenario. However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal. This work introduces an ASIP architecture for the MAP algorithm, based on a dual-clustered VLIW processor. It displays the good performance of application specific designs along with the versatility of processors, which makes it compliant with leading edge standards. The machine deals with multi-operand instructions in an innovative way, the fetching and assertion of data is serialized and the addressing is automatized and transparent for the programmer. The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation

    Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture

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    Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algorithms that are used to implement the baseband processing and the channel decoding. Efficient implementation of multiple wireless standards in mobile terminals requires energy-efficient and flexible hardware. We propose to implement both the baseband processing and channel decoding in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains many processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. We already showed the feasibility to implement the baseband processing of OFDM and WCDMA based communication systems in the MONTIUM. In this paper we implemented two kinds of channel decoders in the same MONTIUM architecture: Viterbi and Turbo decoding
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