Asynchronous Circuit Stacking for Simplified Power Management

As digital integrated circuits (ICs) continue to increase in complexity, new challenges arise for designers. Complex ICs are often designed by incorporating multiple power domains therefore requiring multiple voltage converters to produce the corresponding supply voltages. These converters not only take substantial on-chip layout area and/or off-chip space, but also aggregate the power loss during the voltage conversions that must occur fast enough to maintain the necessary power supplies. This dissertation work presents an asynchronous Multi-Threshold NULL Convention Logic (MTNCL) “stacked” circuit architecture that alleviates this problem by reducing the number of voltage converters needed to supply the voltage the ICs operate at. By stacking multiple MTNCL circuits between power and ground, supplying a multiple of VDD to the entire stack and incorporating simple control mechanisms, the dynamic range fluctuation problem can be mitigated. A 130nm Bulk CMOS process and a 32nm Silicon-on-Insulator (SOI) CMOS process are used to evaluate the theoretical effect of stacking different circuitry while running different workloads. Post parasitic physical implementations are then carried out in the 32nm SOI process for demonstrating the feasibility and analyzing the advantages of the proposed MTNCL stacking architecture

Entanglement Stabilization using Parity Detection and Real-Time Feedback in Superconducting Circuits

Fault tolerant quantum computing relies on the ability to detect and correct errors, which in quantum error correction codes is typically achieved by projectively measuring multi-qubit parity operators and by conditioning operations on the observed error syndromes. Here, we experimentally demonstrate the use of an ancillary qubit to repeatedly measure the $ZZ$ and $XX$ parity operators of two data qubits and to thereby project their joint state into the respective parity subspaces. By applying feedback operations conditioned on the outcomes of individual parity measurements, we demonstrate the real-time stabilization of a Bell state with a fidelity of $F\approx 74\%$ in up to 12 cycles of the feedback loop. We also perform the protocol using Pauli frame updating and, in contrast to the case of real-time stabilization, observe a steady decrease in fidelity from cycle to cycle. The ability to stabilize parity over multiple feedback rounds with no reduction in fidelity provides strong evidence for the feasibility of executing stabilizer codes on timescales much longer than the intrinsic coherence times of the constituent qubits.Comment: 12 pages, 10 figures. Update: Fig. 5 correcte