Applications of the genetic algorithm optimisation approach in the design of high efficiency microwave class E power amplifiers

In this thesis Genetic Algorithm Optimisation Methods (GA) is studied and for the first time used to design high efficiency microwave class E power amplifiers (PAs) and associated load patch antennas. The difficulties of designing high efficiency PAs is that power transistors are highly non linear and classical design techniques only work for resistive loads. There are currently no high efficient and accurate procedures for design high efficiency PAs. To achieve simplified and accurate design procedure, GA and new design quadratic equations are introduced and applied. The performance analysis is based on linear switch models and non linear circuitry push-pull methods. The results of the analytical calculations and experimental verification showed that the power added efficiency (PAE) of the PAs mainly depend on the losses of the active device itself and are nearly independent on the losses of its harmonic networks. Hence, it has been proven that the cheap material PCB FR4 can be used to design high efficiency class E PAs and it also shown that low Q factor networks have only a minor effect on efficiency, allowing a wide bandwidth to be obtained. In additional, a new procedure for designing class E PAs is introduced and applied. The active device (ATF 34143) is used. Good agreement was obtained between predicted analyses and the simulation results (from Microwave Office (AWR) and Agilent ADS software). For the practical realization, class E PAs were fabricated and tested using PCB FR4. The practical results validate computer simulations and the PAE of the class E PAs are more than 71% and Gain is over 3.8 dB when input power (Pin) is equal to 14 dBm at 2 GHz

Methods for Determining Blood Flow Through Intact Vessels of Experimental Animals Under Conditions of Gravitational Stress and in Extra-terrestrial Space Capsules Final Report, 1 Nov. 1960 - 31 Dec. 1964

Electromagnetic blood flow meter to determine blood flow through intact vessels of test animals in gravitational stress and in extraterrestrial space capsule

Feed drive design for numerically controlled machine tools

The various types of feed drive control systems used in numerical control of machine tools have been broadly classified. Further a step by step design has been presented for the feed drive of a numerical contouring control milling machine. The aim has been to develop a consistent strategy for tackling a variety of such problems. Consequently stress has been laid on principles and not on design figures --Abstract, page ii

Two-phase auto-piloted synchronous motors and actuators

Imperial Users onl

Some aspects of high-torque, low-speed, brushless electric motors

Imperial Users onl

On single-amplifier immittance inverters and their use in active filter design

Imperial Users onl

Compensation technique for nonlinear distortion in RF circuits for multi-standard wireless systems

Recent technological advances in the RF and wireless industry has led to the design requirement of more sophisticated devices which can meet stringent specifications of bandwidth, data rate and throughput. These devices are required to be extremely sensitive and hence any external interference from other systems can severely affect the device and the output. This thesis introduces the existing problem in nonlinear components in a multi-standard wireless system due to interfering signals and suggests potential solution to the problem. Advances in RF and wireless systems with emerging new communication standards have made reconfigurablility and tunability a very viable option. RF transceivers are optimised for multi-standard operation, where one band of frequency can act as an interfering signal to the other band. Due to the presence of nonlinear circuits in the transceiver chains such as power amplifiers, reconfigurable and tunable filters and modulators, these interfering signals produce nonlinear distortion products which can deform the output signal considerably. Hence it becomes necessary to block these interfering signals using special components. The main objective of this thesis is to analyse and experimentally verify the nonlinear distortions in various RF circuits such as reconfigurable and tunable filters and devise ways to minimize the overall nonlinear distortion in the presence of other interfering signals. Reconfigurbality and tunablity in filters can be achieved using components such as varactor diodes, PIN diodes and optical switches. Nonlinear distortions in such components are measured using different signals and results noted. The compensation method developed to minimize nonlinear distortions in RF circuits caused due to interfering signals is explored thoroughly in this thesis. Compensation method used involves the design of novel microstrip bandstop filters which can block the interfering signals and hence give a clean output spectrum at the final stage. Recent years have seen the emergence of electronic band gap technology which has “band gap” properties meaning that a bandstop response is seen within particular range of frequency. This concept was utilised in the design of several novel bandstop filters using defected microstrip structure. Novel tunable bandstop filters has been introduced in order to block the unwanted signal. Fixed single-band and dual-band filters using DMS were fabricated with excellent achieved results. These filters were further extended to tunable structures. A dual-band tunable filter with miniaturized size was developed and designed. The designed filters were further used in the compensation technique where different scenarios showing the effect of interfering signals in wireless transceiver were described. Mathematical analysis proved the validation of the use of a bandstop filter as an inter-stage component. Distortion improvements of around 10dB have been experimentally verified using a power amplifier as device under test. Further experimental verification was carried out with a transmitter which included reconfigurable RF filters and power amplifier where an improvement of 15dB was achieved

Efficient and Linear CMOS Power Amplifier and Front-end Design for Broadband Fully-Integrated 28-GHz 5G Phased Arrays

Demand for data traffic on mobile networks is growing exponentially with time and on a global scale. The emerging fifth-generation (5G) wireless standard is being developed with millimeter-wave (mm-Wave) links as a key technological enabler to address this growth by a 2020 time frame. The wireless industry is currently racing to deploy mm-Wave mobile services, especially in the 28-GHz band. Previous widely-held perceptions of fundamental propagation limitations were overcome using phased arrays. Equally important for success of 5G is the development of low-power, broadband user equipment (UE) radios in commercial-grade technologies. This dissertation demonstrates design methodologies and circuit techniques to tackle the critical challenge of key phased array front-end circuits in low-cost complementary metal oxide semiconductor (CMOS) technology. Two power amplifier (PA) proof-of-concept prototypes are implemented in deeply scaled 28- nm and 40-nm CMOS processes, demonstrating state-of-the-art linearity and efficiency for extremely broadband communication signals. Subsequently, the 40 nm PA design is successfully embedded into a low-power fully-integrated transmit-receive front-end module. The 28 nm PA prototype in this dissertation is the first reported linear, bulk CMOS PA targeting low-power 5G mobile UE integrated phased array transceivers. An optimization methodology is presented to maximizing power added efficiency (PAE) in the PA output stage at a desired error vector magnitude (EVM) and range to address challenging 5G uplink requirements. Then, a source degeneration inductor in the optimized output stage is shown to further enable its embedding into a two-stage transformer-coupled PA. The inductor helps by broadening inter-stage impedance matching bandwidth, and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured Pout/PAE at −25 dBc EVM for a 250 MHz-wide, 64-QAM orthogonal frequency division multiplexing (OFDM) signal with 9.6 dB peak-to-average power ratio (PAPR). The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6dB back-off from saturation. To the best of the author’s knowledge, these are the highest measured PAE values among published K- and K a-band CMOS PAs to date. To drastically extend the communication bandwidth in 28 GHz-band UE devices, and to explore the potential of CMOS technology for more demanding access point (AP) devices, the second PA is demonstrated in a 40 nm process. This design supports a signal radio frequency bandwidth (RFBW) >3× the state-of-the-art without degrading output power (i.e. range), PAE (i.e. battery life), or EVM (i.e. amplifier fidelity). The three-stage PA uses higher-order, dual-resonance transformer matching networks with bandwidths optimized for wideband linearity. Digital gain control of 9 dB range is integrated for phased array operation. The gain control is a needed functionality, but it is largely absent from reported high-performance mm-Wave PAs in the literature. The PA is fabricated in a 1P6M 40 nm CMOS LP technology with 1.1 V supply, and achieves Pout/PAE of +6.7 dBm/11% for an 8×100 MHz carrier aggregation 64-QAM OFDM signal with 9.7 dB PAPR. This PA therefore is the first to demonstrate the viability of CMOS technology to address even the very challenging 5G AP/downlink signal bandwidth requirement. Finally, leveraging the developed PA design methodologies and circuits, a low power transmit-receive phased array front-end module is fully integrated in 40 nm technology. In transmit-mode, the front-end maintains the excellent performance of the 40 nm PA: achieving +5.5 dBm/9% for the same 8×100 MHz carrier aggregation signal above. In receive-mode, a 5.5 dB noise figure (NF) and a minimum third-order input intercept point (IIP₃) of −13 dBm are achieved. The performance of the implemented CMOS frontend is comparable to state-of-the-art publications and commercial products that were very recently developed in silicon germanium (SiGe) technologies for 5G communication