Optimization of Power Consumption for the Design of 802.11n MIMO_OFDM System

في انظمة الاتصالات الحديثة توجد طرق مختلفة لتحسين أداء التقنيات السابقة التقليدية والتي تتعلق بمعالجة البيانات المرسلة والمستلمة من حيث زيادة سرعة عمليات الارسال والاستلام حيث انه البطئ في هذه العملية يؤدي الى فقدان الكثير من المعلومات المرسلة لذا فانه من الضروري تحسين تقنية تعدد الإرسال بتقسيم التردد المتعامد OFDM)) لأنه يعتبر في اولوية النظام اللاسلكي الذي يتضمن بيانات الأمن وموثوقية بيانات الإرسال. تطبيقات الاتصالات اللاسلكية مهم في هذا المجال من أجل تحسين وزيادة سرعة عملية معالجة البيانات والذي يؤدي بدوره بشكل مهم إلى تقليل مستوى استهلاك الطاقة للنظام. أن تصميم وتنفيذ الدوائر المتكاملة بأستخدام مصفوفة البوابات المبرمجة (FPGA) جاء لأجل تحسين اداء نظام الارسال والاستلام لل 802.11n في تقسيم التردد المتعامد حيث تم تصميم نظام (OFDM_MIMO) 6X6 بأستخدام المحاكاة في برنامج الماتلاب ومن ثم استخدام لغة البرمجة VHDL لغرض استخدامها في برمجة مصفوفة البوابات المبرمجة (FPGA) حيث تم استخدام نوع Xilinx Spartan 3 XC3S200 وفي النتائج تم الحصول على أقل أستهلاك للطاقة الكلية للنظام حيث سجلت  94mW مقارنة مع عمل سابق كانت سجلت mW136 أي قلت كمية الطاقة المستهلكة بنسبة 30.8%.In modern systems communication, different methods have been improved to change the prior imitative techniques that process communication data with high speed. It is necessary to improve (OFDM) Orthogonal Frequency Division Multiplexing technique because the development in the guideline communication of wireless system which include security data and transmission data reliability. The applications communications of wireless is important to develop in order to optimize the process of communication leads to reduce the level consumption energy of the output level signal. The architecture of VLSI is used to optimize the performance transceiver in 802.11 n OFDM-MIMO systems, this idea concentrate on the design of 6x6 MIMO_OFDM system in software simulink of MATLAB then using generator system for transfer to code of VHDL and applying in FPGA Xilinx Spartan 3 XC3S200 . The modelsim used to get the simulation while Xilinx power estimator is used to calculate power. The results registered total power consumption about 94mW while compared with previous work  was 136mW which means a high reduction of about 30.8%

The Digital Design and Synthesis of Delay Doppler Maps in GNSS Remote Sensing Receivers

Global Navigation Satellite Systems (GNSS) are satellite based systems primarily capable of determining the location of receivers on the Earth. However, these systems can also receive and process bistatically surface reflected signals, studying the scattering from the signal off the reflection surface. In order to achieve these results, accurate and fast technology are necessary. In this work, a Delay-Doppler mapping module of a GNSS system has been implemented in VHDL and synthesized on FPGA Xilinx-Virtex 6 to map the delay and frequency domains of Earth scattered signals. The designed system presents high timing performance to provide quick and accurate measurements. In this work, a FFT based GNSS mapping algorithms has been designed to process raw samples GNSS data. The remote sensing module has been implemented, generating all the 32 possible C/A codes and then processing the received signal for each of the 32 C/A codes in a pipelined circuit. Once the GNSS power signals have been detected, a final detector is used to compare all the GNSS power signals found with a magnitude twice the noise and with the highest peak to detect the best candidate signal for the Delay Doppler Map (DDM). Different timing delay ranges and Doppler frequency ranges have been considered to compare the performance of the mapping algorithm. The use of an FPGA based algorithm permits significantly higher performance and greater flexibility than software based solutions and opens up the GNSS remote sensing application for integration into real-time instruments

System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing

This dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications. Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance. This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB. Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy). The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption. Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude

Rotation Measure Synthesis of Galactic Polarized Emission with the DRAO 26-m Telescope

Radio polarimetry at decimetre wavelengths is the principal source of information on the Galactic magnetic field. The diffuse polarized emission is strongly influenced by Faraday rotation in the magneto-ionic medium and rotation measure is the prime quantity of interest, implying that all Stokes parameters must be measured over wide frequency bands with many frequency channels. The DRAO 26-m Telescope has been equipped with a wideband feed, a polarization transducer to deliver both hands of circular polarization, and a receiver, all operating from 1277 to 1762 MHz. Half-power beamwidth is between 40 and 30 arcminutes. A digital FPGA spectrometer, based on commercially available components, produces all Stokes parameters in 2048 frequency channels over a 485-MHz bandwidth. Signals are digitized to 8 bits and a Fast Fourier Transform is applied to each data stream. Stokes parameters are then generated in each frequency channel. This instrument is in use at DRAO for a Northern sky polarization survey. Observations consist of scans up and down the Meridian at a drive rate of 0.9 degree per minute to give complete coverage of the sky between declinations -30 degree and 90 degree. This paper presents a complete description of the receiver and data acquisition system. Only a small fraction of the frequency band of operation is allocated for radio astronomy, and about 20 percent of the data are lost to interference. The first 8 percent of data from the survey are used for a proof-of-concept study, which has led to the first application of Rotation Measure Synthesis to the diffuse Galactic emission obtained with a single-antenna telescope. We find rotation measure values for the diffuse emission as high as approximately 100 rad per square metre, much higher than recorded in earlier work.Comment: Accepted for publication in The Astronomical Journa

Continuous Integration for Fast SoC Algorithm Development

Digital systems have become advanced, hard to design and optimize due to ever-growing technology. Integrated Circuits (ICs) have become more complicated due to complex computations in latest technologies. Communication systems such as mobile networks have evolved and become a part of our daily lives with the advancement in technology over the years. Hence, need of efficient, reusable and automated processes for System-on-a-Chip (SoC) development has been increased. Purpose of this thesis is to study and evaluate currently used SoC development processes and presents guidelines on how these processes can be streamlined. The thesis starts by evaluating currently used SoC development flows and their advantages and disadvantages. One important aspect is to identify step which cause duplication of work and unnecessary idle times in SoC development teams. A study is conducted and input from SoC development experts is taken in order to optimize SoC flows and use of Continuous Integration (CI) system. An algorithm model is implemented that can be used in multiple stages of SoC development at adequate complexity and is “easy enough” to be used for a person not mastering the topic. The thesis outcome is proposal for CI system in SoC development for accelerating the speed and reliability of implementing algorithms to RTL code and finally into product. CI system tool is also implemented to automate and test the model design so that it also remains up to date

Desenvolvimento em VHDL da camada física de um transmissor 4G

The LTE and LTE-Advanced technologies are standards to the fourth mobile generation, or 4G. The planned successor of this mobile generation is 5G, which will be based on 5G-New Radio (5G-NR) standard. The 5G technology is on an initial phase of deployment. One of its features that are essential in this initial phase is the support for 4G communications, because many of the mobile devices currently in use do not have support for 5G communications. This support is made possible if there is an implementation where 4G and 5G networks both coexist with each other. In the future, with the increasing usage of mobile devices with 5G support, there will be a gradual migration of 4G networks to 5G, releasing frequency spectrums currently reserved for 4G so that those can be occupied by 5G. The data transmissions in 4G require quite a lot of the processing capacity of all systems within the mobile network. For 5G, the data transmissions, in terms of traffic volume and speed, are larger than 4G transmissions, requiring new systems to be implemented, to allow the processing of larger quantities of data. Implementation in hardware of a 4G Uplink transmission chain, at the physical layer level PHY-Low, will allow the optimization of certain processes that a CPU could handle, reducing CPU usage and time spent on processing. The use of FPGAs makes this possible, as FPGAs can perform parallel tasks simultaneously and perform digital signal processing. The purpose of this dissertation is the modelling of a 4G LTE Uplink transmitter, at the physical layer level. Then, synthesizable VHDL code is generated from the modeled system, which can be eventually implemented in FPGAs. The modelling of the system is made in Simulink, a tool inside the MATLAB software, which allows for modelling, simulating and analyzing systems in a graphic environment and has applications in control systems and digital signal processing. The VHDL code is generated from HDL Coder, another tool in MATLAB software, generating synthesizable Verilog and VHDL code, from the MATLAB functions and Simulink models. The results obtained of processed data from the system are analyzed and validated, comparing the reference data generated from Wireless Waveform Generator toolbox in MATLAB.A tecnologia LTE e LTE-Advanced são standards da quarta geração de comunicações moveis atuais, ou 4G. Futuramente, o 5G marca a próxima geração de comunicações moveis, segundo o standard 5G-New Radio (5GNR). A tecnologia 5G encontra-se numa fase inicial de implementação, sendo que nessa fase uma das suas características fundamentais é o suporte para comunicações 4G, pois muitos dos dispositivos moveis usados atualmente não possuem suporte para comunicações 5G. Este suporte para 4G é tornado possível, se for feita uma implementação onde as redes 4G e 5G se encontrem em coexistência. No futuro, com o aumento do uso de dispositivos moveis com suporte para 5G, haverá uma migração gradual de redes 4G para 5G, libertando os espectros de frequências reservados atualmente para o 4G para serem ocupados pelo 5G. As transmissões de dados no 4G exigem bastante da capacidade de processamento de todos os sistemas da rede movel. Para o 5G, as transmissões de dados tem volumes de tráfego e velocidades maiores do que as transmissões de dados 4G, fazendo com que novos sistemas tenham de ser implementados para poder processar maiores quantidades de dados. A implementação em hardware da cadeia de transmissão 4G Uplink, ao nível da camada física PHY-Low, permitirá a otimização de certos processos que um CPU poderia lidar, diminuindo o uso do CPU e o tempo gasto em processamento. O uso de FPGAs torna isto possível, tendo em conta que podem realizar tarefas em paralelo, em modo simultâneo, e fazer processamento digital de sinal. O objetivo desta dissertação assenta na modelação de um transmissor 4G LTE Uplink, ao nível da camada física. Depois, é gerado código VHDL sintetizável a partir do sistema modelado, que eventualmente será implementada em FPGAs. A modelação do sistema é feito em Simulink, uma ferramenta no software do MATLAB, que permite modelar, simular e analisar sistemas num ambiente gráfico e tem aplicações para sistemas de controlo e processamento digital de sinal. O código VHDL é gerado a partir do HDL Coder, uma outra ferramenta no software do MATLAB, que gera Verilog e VHDL sintetizáveis, a partir de funções MATLAB e de modelos Simulink. Os resultados obtidos dos dados processados pelo sistema são analisados e validados, comparando com os dados de referência obtidos a partir da toolbox Wireless Waveform Generator do MATLAB.Mestrado em Engenharia Eletrónica e Telecomunicaçõe

Design of a Mobile Transceiver for Precision Indoor Location

This thesis documents the design and implementation process for the next generation of the WPI Precision Personnel Location (PPL) system hardware. The driving goal of the new hardware was to support a new method of radio frequency location developed at WPI referred to as Transactional Array Reconciliation Tomography (TART). This new method is based on a time of arrival (TOA) technique as opposed to the previous Singular Value Array Reconciliation Tomography (SART), which uses time difference of arrival (TDOA). The use of a TOA method requires additional timing information and necessitates a bidirectional (transmit and receive) multicarrier transaction. The design of the new transceiver that can function as both a mobile locator and a static reference unit is the main focus of this thesis. This redesign also addressed previous hardware issues that have been exposed through extensive use in real world testing

An FPGA implementation of OFDM transceiver for LTE applications

The paper presents a real-time transceiver using an Orthogonal Frequency-Division Multiplexing (OFDM) signaling scheme. The transceiver is implemented on a Field- Programmable Gate Array (FPGA) through Xilinx System Generator for DSP and includes all the blocks needed for the transmission path of OFDM. The transmitter frame can be reconfigured for different pilot and data schemes. In the receiver, time-domain synchronization is achieved thr ough a joint maximum likelihood (ML) symbol arrival-time and carrier frequency offset (CFO) estimator through the redundant information contained in the cyclic prefix (CP). A least-squares channel estimation retrieves the channel state information and a simple zero-forcing scheme has been implemented for channel equalization. Results show that a rough implementation of the signal path can be impleme nted by using only Xilinx System Generator for DSP

Python based FPGA design-flow

This dissertation undertakes to establish the feasibility of using MyHDL as a basis on which to develop an FPGA-based DSP tool-ow to target CASPER hardware. MyHDL is an open-source package which enables Python to be used as a hardware definition and verification language. As Python is a high-level language, hardware designers can use it to model and simulate designs, without needing detailed knowledge of the underlying hardware. MyHDL has the ability to convert designs to Verilog or VHDL allowing it to integrate into the more traditional design-ow. The CASPER tool- ow exhibits limitations such as design environment instability and high licensing fees. These shortcomings are addressed by MyHDL. To enable CASPER to take advantage of its powerful features, MyHDL is incorporated into a next generation tool-ow which enables high-level designs to be fully simulated and implemented on the CASPER hardware architectures

High-Performance Computing for SKA Transient Search: Use of FPGA based Accelerators -- a brief review

This paper presents the High-Performance computing efforts with FPGA for the accelerated pulsar/transient search for the SKA. Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several 100s of beams, and processing the data in the SKA real-time pulsar search pipelines. A brief account of the different architectures of the accelerators, primarily the new generation Field Programmable Gate Array-based accelerators, showing their critical roles to achieve high-performance computing and in handling the enormous data volume problems of the SKA is presented here. It also presents the power-performance efficiency of this emerging technology and presents potential future scenarios.Comment: Accepted for JoAA, SKA Special issue on SKA (2022