An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature

INTRODUCING AN OPTIMAL QCA CROSSBAR SWITCH FOR BASELINE NETWORK

Crossbar switch is the basic component in multi-stage interconnection networks. Therefore, this study was conducted to investigate performance of a crossbar switch with two multiplexers. The presented crossbar switch was simulated using quantum-dot cellular automata (QCA) technology and QCA Designer software, and was studied and optimized in terms of cell number, occupied area, number of clocks, and energy consumption. Using the provided crossbar switch, the baseline network was designed to be optimal in terms of cell number and occupied area. Also, the number of input states was investigated and simulated to verify accuracy of the baseline network. The proposed crossbar switch uses 62 QCA cells and the occupied area by the switch is equal to 0.06µm2 and its latency equals 4 clock zones, which is more efficient than the other designs. In this paper, using the presented crossbar switch, the baseline network was designed with 1713 cells, and occupied area of 2.89µm2

DESIGN OF NOVEL MULTIPLEXER CIRCUITS IN QCA NANOCOMPUTING

Quantum-dot Cellular Automata (QCA) technology is a promising alternative nano-scale technology for CMOS technology. In digital circuits, a multiplexer is one of the most important components. In this study, an efficient and single layer 2 to 1 QCA multiplexer circuit is proposed using majority gate and inverter gate. In addition, efficient 4 to 1 and 8 to 1 QCA multiplexer circuits are implemented using this 2 to 1 multiplexer circuit. The developed multiplexer circuits are implemented in QCADesigner tool. According to the results, the developed 2 to 1, 4 to 1, and 8 to 1 multiplexer circuits utilize 16 (0.01μm2), 96 (0.11μm2), and 286 (0.43μm2) QCA cell (area). The results demonstrate that the proposed 8 to 1 multiplexer circuit reduces the cost by about 25%-99% compared to the existing multiplexer circuits

Design of Power-Efficient Structures of the CAM Cell using a New Approach in QCA Nanoelectronics Technology

Quantum-dot Cellular Automata (QCA) is a new emerging nano-electronic technology. Owing to its many fa-vorable features such as low energy requirements, high speed, and small size, QCA is being actively suggested as a future CMOS replacement by researchers. Many digital circuits have been introduced in QCA technology, most of them aiming to reach the function with optimum construction in terms of area, cell count and power consumption. The memory circuit is the main building block in the digital system therefore the researchers paid attention to design the memory cells with minimum requirements. In this paper, a new methodology is intro-duced to design two forms of CAM cell. The proposed designs required two 2:1 multiplexers, one OR gate and one inverter. The first proposed design reduces the power consumption by 53.3%, 35% and 25.9% at (0.5 Ek, 1 Ek, and 1.5 Ek) while the second design by 53.2%, 31.9% and 20.5% (0.5 Ek, 1 Ek, and 1.5 Ek) respectively

Design of Novel Efficient Multiplexer Architecture for Quantum-dot Cellular Automata

One of the promising emerging technology at nanoscale level to replace the conventional CMOS technology is Quantum-dot Cellular Automata (QCA). It has several advantages compared to conventional CMOS technology. Whereas multiplexers play a vital role in digital circuit implementations, this paper presents and evaluates a modular design methodology to build the high-performance 2n:1 multiplexer. An efficient 2:1 QCA multiplexer architecture is proposed as the basic logic unit, which is utilized to present new and efficient 4:1, and 8:1 QCA multiplexer architectures. The proposed architectures have been implemented on the QCADesigner version 2.0.1. Our implementation results show that the proposed QCA multiplexer architectures have the best performance compared to other multiplexer architectures and outperform most of them in terms of area and clock zones

MF-RALU: design of an efficient multi-functional reversible arithmetic and logic unit for processor design on field programmable gate array platform

Most modern computer applications use reversible logic gates to solve power dissipation issues. This manuscript uses an efficient multi-functional reversible arithmetic and logical unit (MF-RALU) to perform 30 operations. The 32-bit MF-RALU includes arithmetic, logical, complement, shifters, multiplexers, different adders, and multipliers. The multi-bit reversible multiplexers are used to construct the MF-RALU structure. The Reduced instruction set computer (RISC) processor is designed to realize the functionality of the MF-RALU. The MF-RALU can perform its operation in a single clock cycle. The 1-bit RALU is developed and compared with existing approaches with improvements in performance metrics. The 32-bit reversible arithmetic units (RAUs) and reversible logical units (RLUs) are constructed using 1-bit RALU. The MF-RALU and RISC processor are synthesized individually in the Vivado environment using Verilog-HDL and implemented on Artix-7 field programmable gate array (FPGA). The MF-RALU utilizes a <11% chip area and consumes 332 mW total power. The RISC processor utilizes a <3% chip area and works at 483 MHZ frequency by consuming 159 mW of total power on Artix-7 FPGA

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture