Oxide bypassed power MOSFET devices

Master'sMASTER OF ENGINEERIN

GaN-based power devices: Physics, reliability, and perspectives

Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semicon- ductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spon- taneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high- voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench- structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main proper- ties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics

Design, simulation, fabrication and characterisation of 4H-SiC trench MOSFETs

For solid-state power devices, there exists need for a material with a higher band gap which will result in a higher critical electric field, improved power efficiency and thermal performance. This has resulted in the use of Silicon Carbide (SiC) as a serious alternative to Silicon for power devices. SiC trench MOSFETs have attracted major attention in recent years because of 1) lower on resistance by eliminating the JFET effect which exists in lateral MOSFETs, 2) higher channel density which lowers the threshold voltage and 3) reduction of the required surface area because of the vertical channel. These advantages allow faster switching speeds and the potential for a higher density of devices leading to more compact modules. This work was focused on fabrication of the first generation of 4H-SiC trench MOSFETs in Warwick University. Two main goals were achieved in this work: a comprehensive understanding of fabrication of trenches in 4H-SiC and fabrication of first generation of 4H-SiC trench MOSFET with mobility as high as 3

In-situ Oxide, GaN interlayer based vertical trench MOSFET (OG-FET)

The surge in world-wide energy consumption places a growing need for highly efficient power electronics for generation, transportation, and utilization of electricity. With the advent of new markets such as electric vehicles, PV solar inverters, the market for these power electronics components is predicted to reach $15 billion by 2020. Silicon-based devices are most commonly used in traditional power electronics applications, however, wide bandgap semiconductors such as gallium nitride (GaN) are more efficient and thus, useful for future energy applications.Consequently, Gallium Nitride (GaN) based power devices have gained increased attention in recent years. For 600 V class power devices, lateral GaN high electron mobility transistors are available today. However, it is generally considered that for high voltage/high current applications (>900V/100 A), vertical device structures might be more suitable owing to their capability of achieving lower specific on-resistance and high breakdown voltage simultaneously.Amongst numerous vertical device structures, the trench MOSFET is an attractive device structure to reduce on-resistance due to the capability of high cell density and the absence of a JFET region. However, high channel resistance in trench MOSFETs due to poor electron mobility in the channel creates reliability issues as a higher gate bias needs to be applied to reduce the channel resistance.In this dissertation work, we developed a novel device design (called OG-FET) to enhance the channel mobility and therefore, lower the channel-resistance for the trench MOSFET structure while maintaining normally-off operation and same breakdown voltage. In OG-FET, a GaN interlayer is regrown followed by in-situ dielectric deposition via MOCVD on the n-p-n trenched structure to enhance the channel mobility. In addition, the in-situ gate-dielectric growth onto the GaN interlayer allows this device to achieve lower interface trap density compared to devices with ex-situ dielectrics deposited onto the trenched structure. This thesis discusses the OG-FET device design, growth and fabrication process alongside device results and analysis. With sustained efforts, OG-FETs with high DC performance were achieved. The OG-FETs demonstrated threshold voltage between 1-4 V, breakdown voltage beyond 1 kV with a low on-resistance between 1.5-3 mΩ.cm2. The on-resistance values were achieved at a relatively low gate bias (~12 V-15 V) and low gate-dielectric field (~2-3 MV/cm) compared to conventional GaN trench MOSFETs. These results are promising for the future application of OG-FETs for high voltage and high-power electronics

The 2018 GaN Power Electronics Roadmap

Gallium nitride (GaN) is a compound semiconductor that has tremendous potential to facilitate economic growth in a semiconductor industry that is silicon-based and currently faced with diminishing returns of performance versus cost of investment. At a material level, its high electric field strength and electron mobility have already shown tremendous potential for high frequency communications and photonic applications. Advances in growth on commercially viable large area substrates are now at the point where power conversion applications of GaN are at the cusp of commercialisation. The future for building on the work described here in ways driven by specific challenges emerging from entirely new markets and applications is very exciting. This collection of GaN technology developments is therefore not itself a road map but a valuable collection of global state-of-the-art GaN research that will inform the next phase of the technology as market driven requirements evolve. First generation production devices are igniting large new markets and applications that can only be achieved using the advantages of higher speed, low specific resistivity and low saturation switching transistors. Major investments are being made by industrial companies in a wide variety of markets exploring the use of the technology in new circuit topologies, packaging solutions and system architectures that are required to achieve and optimise the system advantages offered by GaN transistors. It is this momentum that will drive priorities for the next stages of device research gathered here

Design and fabrication of superjunction power MOSFET devices

Ph.DDOCTOR OF PHILOSOPH

High Efficiency IGBTs through Novel Three-Dimensional Modelling and New Architectures

New Insulated Gate Bipolar Transistor (IGBT) designs are reliant on simulation tools, such as Sentaurus technology computer-aided design (TCAD) models, which allow for rapid device development that could not be achieved by manufacturing prototypes due to the cost and time associated with fabrication. These simulations are, though, computationally expensive and typically most design engineers develop these TCAD models only in two dimensions. This leads to inaccuracies in the model output since manufactured transistors are inherently three-dimensional (3D). Based upon a commercial IGBT, this thesis begins by outlining the development of a 3D TCAD model using design details provided by the manufacturer. Large variations between the experimental data from the manufactured device and the simulation model lead to the discovery of widespread birds-beaking within the IGBT – an uncontrollable processing defect that the manufacturer was unaware of. This thesis presents a new simulation technique to account for this processing error while minimising computational effort and investigates the consequence of this birds-beak on the reliability of the device. The verified 3D IGBT model was also used to determine an optimum cell design that considered critical 3D effects omitted from previous studies. An extensive literature review for the Reverse-Conducting IGBT (RC-IGBT) is provided. It is shown that despite the benefits of the RC-IGBT, the device suffers from many undesirable design trade-offs that have prevented its widespread use. The RC-IGBT designs that have currently been proposed in literature, either present a trade-off in performance, an inability to be manufactured, or a requirement for a custom gate drive. This thesis presents a new RC-IGBT concept, the ‘Dual Implant SuperJunction (SJ) RC-IGBT’ that addresses these concerns and is manufacturable using current state of the art techniques. The concept and proposed manufacturing method enables, for the first time, a full SuperJunction structure to be achieved in a 1.2kV device. In addition, an investigation into a coordinated switching scheme using both a silicon IGBT and silicon-carbide MOSFET was undertaken, which aimed to improve turn-off losses within the IGBT without sacrificing on-state losses. Thermal modelling of the power devices switching under inductive load was explored as the system was optimised to use a SiC MOSFET in excess of its nominal ratings, reducing the overall system cost.EPSRC Doctoral Training Partnership scheme (grant RG75686

Development of a fault tolerant MOS field effect power semiconductor switching transistor

This work describes the development of a semiconductor switch to replace an electromechanical contactor as used within the electrical power distribution system of the More Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The MEA is safety critical and therefore requires highest reliability components and systems, but subsequent to a short circuit load fault the electro-mechanical contactor switch often welds shut. This risk is increased when using high discharge energy lithium ion dc batteries. Predominately the semiconductor switch controls inductive loads and is required to safely turn off current of up to 10 times the nominal level during sporadic load fault events. The switch requires the lowest static loss (lowest on state resistance), but also the lowest dynamic loss (losses due to the switching event). Presently, unipolar devices provide the lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which is sized to suit the fault current, but at relatively high cost in terms of silicon area. The resultant area is typically achieved by several die connected in parallel, unfortunately, such a solution suffers from current share imbalance and the potential of cascade die failure. The use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid which proves challenging if the load current is to be shared appropriately during fault switching in order to prevent failure. Some form of single MOS (Metal Oxide Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore required to ensure highest reliability through a non latching design which offers lowest losses under all conditions and achieves an even temperature distribution. In this work the novel concept of the integrated hybrid device has been investigated at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises a novel merged Schottky p-type injector to provide self biased entry into a reduced static loss bipolar state in the event of high fault current. The device achieves a specific on state resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon limit line and requires half the area of a traditional unipolar MOSFET to conduct fault current. During comparative standard unclamped inductive switching trials, the hybrid device provides a self clamping action which enables increased inductive energy switching (higher inductance and/or higher load current), relative to that achieved by either the MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically >10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device is latch up free across the operational temperature range of T=233 K to 400 K. A viable charge balanced structure to increase the BV rating to approximately 600 V is also proposed. The resulting performance of the single gated, self biased, hybrid, utilising a novel merged Schottky/P type injector, could lead to a new class of rugged MOS gated power switching devices in silicon and potentially silicon carbide

Advanced Scanning Tunneling Microscopy for Nanoscale Analysis of Semiconductor Devices

Significant attention has been addressed to high-spatial resolution analysis of modern sub-100-nm electronic devices to achieve new functions and energy-efficient operations. The chapter presents a review of ongoing research on charge carrier distribution analysis in nanoscale Si devices by using scanning tunneling microscopy (STM) employing advanced operation modes: a gap-modulation method, a molecule-assisted probing method, and a dual-imaging method. The described methods rely on detection and analysis of tunneling current, which is strongly localized within an atomic dimension. Representative examples of applications to nanoscale analysis of Si device cross-sections and nanowires are given. Advantages, difficulties, and limitations of the advanced STM methods are discussed in comparison with other techniques used in a field of device metrology