A proportional plus a hysteretic term control design: a throttle experimental emulation to wind turbines pitch control

Pitch control is a relevant issue in wind turbines to properly operate the angle of the blades. Therefore, this control system pitches the blades usually a few degrees every time the wind changes in order to keep the rotor blades at the required angle thus controlling the rotational speed of the turbine. All the same time, the control of the pitch angle is not easy due to the system behavior being highly nonlinear. Consequently, the main objective of this paper is to depict an easy to implement control design based on a proportional controller and a hysteretic term to an emulator pitch control system in wind turbines. This emulator is just an automotive throttle device. This mechanical body dynamically captures some hard non-linearities presented in pitch wind turbine mechanisms, such as backlash, asymmetrical non-lineal effects, friction, and load variations. Even under strong non-linear effects that are difficult to model, a proportional controller and a hysteretic term may satisfy the main control design objective. Hence, a recent control design is developed and applied to a throttle system. We invoke the Lyapunov theory to confirm stability of the resultant closed-loop system. In addition, the proposed control approach is completely implemented by using operational amplifiers. Hence, no digital units are required at all. Moreover, the cost of the developed experimental platform and its outcomes are inexpensive. According to the experimental results, the controller performance seems acceptable, and validating of the control contribution too. For instance, a settling-time of about 0.03 s to a unit step-response is obtained.Peer ReviewedPostprint (published version

Co-simulation techniques based on virtual platforms for SoC design and verification in power electronics applications

En las últimas décadas, la inversión en el ámbito energético ha aumentado considerablemente. Actualmente, existen numerosas empresas que están desarrollando equipos como convertidores de potencia o máquinas eléctricas con sistemas de control de última generación. La tendencia actual es usar System-on-chips y Field Programmable Gate Arrays para implementar todo el sistema de control. Estos dispositivos facilitan el uso de algoritmos de control más complejos y eficientes, mejorando la eficiencia de los equipos y habilitando la integración de los sistemas renovables en la red eléctrica. Sin embargo, la complejidad de los sistemas de control también ha aumentado considerablemente y con ello la dificultad de su verificación. Los sistemas Hardware-in-the-loop (HIL) se han presentado como una solución para la verificación no destructiva de los equipos energéticos, evitando accidentes y pruebas de alto coste en bancos de ensayo. Los sistemas HIL simulan en tiempo real el comportamiento de la planta de potencia y su interfaz para realizar las pruebas con la placa de control en un entorno seguro. Esta tesis se centra en mejorar el proceso de verificación de los sistemas de control en aplicaciones de electrónica potencia. La contribución general es proporcionar una alternativa a al uso de los HIL para la verificación del hardware/software de la tarjeta de control. La alternativa se basa en la técnica de Software-in-the-loop (SIL) y trata de superar o abordar las limitaciones encontradas hasta la fecha en el SIL. Para mejorar las cualidades de SIL se ha desarrollado una herramienta software denominada COSIL que permite co-simular la implementación e integración final del sistema de control, sea software (CPU), hardware (FPGA) o una mezcla de software y hardware, al mismo tiempo que su interacción con la planta de potencia. Dicha plataforma puede trabajar en múltiples niveles de abstracción e incluye soporte para realizar co-simulación mixtas en distintos lenguajes como C o VHDL. A lo largo de la tesis se hace hincapié en mejorar una de las limitaciones de SIL, su baja velocidad de simulación. Se proponen diferentes soluciones como el uso de emuladores software, distintos niveles de abstracción del software y hardware, o relojes locales en los módulos de la FPGA. En especial se aporta un mecanismo de sincronizaron externa para el emulador software QEMU habilitando su emulación multi-core. Esta aportación habilita el uso de QEMU en plataformas virtuales de co-simulacion como COSIL. Toda la plataforma COSIL, incluido el uso de QEMU, se ha analizado bajo diferentes tipos de aplicaciones y bajo un proyecto industrial real. Su uso ha sido crítico para desarrollar y verificar el software y hardware del sistema de control de un convertidor de 400 kVA

Design and application of electromechanical actuators for deep space missions

This progress report documents research and development efforts performed from August 16, 1993 through August 15, 1994 on NASA Grant NAG8-240, 'Design and Application of Electromechanical Actuators for Deep Space Missions.' Since the submission of our last progress report in February 1994, our efforts have been almost entirely focused on final construction of the test stand and experiment design. Hence, this report is dedicated solely to these topics. However, updates on our research personnel and our health monitoring and fault management efforts are provided in this summary. Following this executive summary are two report sections. The first is devoted to the motor drive being constructed for the test stand. The thrust of the next section is the mechanical and hydraulic design and construction based on the planned experimental requirements. Following both major sections are three appendices

A fast remotely operable digital twin of a generic electric powertrain for geographically distributed hardware-in-the-loop simulation testbed

The automotive industry today is seeing far-reaching and portentous changes that will change the face of it in the foreseeable future. Digitalisation and Electrification are two of the key megatrends that is changing the way vehicles are developed and produced. A recent development in R&D process is the Hardware-in-the-Loop (HIL) method that uses a hybrid approach of testing a physical prototype immersed in a virtual environment, which is nowadays being creatively re-applied towards geographically separated multi-centre testing strategies, that suits the horizontally integrated and supply-chain driven industry very well. Geographical separation entails the deployment of a “Digital Twin” in remote centre(s) participating in multi-centre testing. This PhD aims to produce a highly robust, efficient, and rapidly computable Digital Twin of a generic electric powertrain using the multi-frequency averaging (MFA) technique that has been extended for variable frequency operation. This PhD also aims to commission a local HIL simulation testbed for a generic electric power inverter testing. The greater goal is to co-simulate the local HIL centre testing a prototype inverter, and its Digital Twin in a different location “twinning” the prototype inverter as best as possible. A novel approach for the Digital Twin has been proposed that employs Dynamic Phasors to solve the system in the frequency domain. An original method of multiplication of two signals in the frequency domain has been proposed. The resultant model has been verified against an equivalent time domain switching model and shown to outperform appreciably. A distinctive advantage the MFA Digital Twin offers is the “fidelity customisability”; based on application, the Twin can be set to compute a low (or high)-fi model at different computational cost. Finally, a novel method of communicating high-speed motor shaft position information using a low-speed processing system has been developed and validated. This has been applied to run real-life HIL simulation cycles on a test inverter and effects studied. The two ends of a multi-HIL testbed, i.e., local HIL environment for an inverter, and its Digital Twin, has been developed and validated. The last piece of the puzzle, i.e., employing a State Convergence algorithm to ensure the Digital Twin is accurate duplicating the performance of its “master”, is required to close the loop. Several ideas and process plans have been proposed to do the same

Design and Testing of Electronic Devices for Harsh Environments

In this thesis an overview of the research activity focused on development, design and testing of electronic devices and systems for harsh environments has been reported. The scope of the work has been the design and validation flow of Integrated Circuits operating in two harsh applications: Automotive and High Energy Physics experiments. In order to fulfill the severe operating electrical and environmental conditions of automotive applications, a systematic methodology has been followed in the design of an innovative Intelligent Power Switch: several design solutions have been developed at architectural and circuital level, integrating on-chip selfdiagnostic capabilities and full protection against high voltage and reverse polarity, effects of wiring parasitics, over-current and over-temperature phenomena. Moreover current slope and soft start integrated techniques has ensured low EMI, making the Intelligent Power Switch also configurable to drive different interchangeable loads efficiently. The innovative device proposed has been implemented in a 0.35 μm HV-CMOS technology and embedded in mechatronic 3rd generation brush-holder regulator System-on-Chip for an automotive alternator. Electrical simulations and experimental characterization and testing at componentlevel and on-board system-level has proven that the proposed design allows for a compact and smart power switch realization, facing the harshest automotive conditions. The smart driver has been able to supply up to 1.5 A to various types of loads (e.g.: incadescent lamp bulbs, LED), in operating temperatures in the wide range -40 °C to 150 °C, with robustness against high voltage up to 55 V and reverse polarity up to -15 V. The second branch of research activity has been framed within the High Energy Physics area, leading to the development of a general purpose and flexible protocol for the data acquisition and the distribution of Timing, Trigger and Control signals and its implementation in radiation tolerant interfaces in CMOS 130 nm technology. The several features integrated in the protocol has made it suitable for different High Energy Physics experiments: flexibility w.r.t. bandwidth and latency requirements, robustness of critical information against radiation-induced errors, compatibility with different data types, flexibility w.r.t the architecture of the control and readout systems, are the key features of this novel protocol. Innovative radiation hardening techniques have been studied and implemented in the test-chip to ensure the proper functioning in operating environments with a high level of radiation, such as the Large Hadron Collider at CERN in Geneva. An FPGA-based emulator has been developed and, in a first phase, employed for functional validation of the protocol. In a second step, the emulator has been modified as test-bed to assess the Transmitter and Receiver interfaces embedded on the test-chip. An extensive phase of tests has proven the functioning of the interfaces at the three speed options, 4xF, 8xF and 16xF (F = reference clock frequency) in different configurations. Finally, irradiation tests has been performed at CERN X-rays irradiation facility, bearing out the proper behaviour of the interfaces up to 40 Mrad(SiO2)

Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

Modeling and Control of Power Electronics Interfaced Load for Transmission Power Network Analysis

The penetration level of power electronics (PE) interfaced loads has been gradually increasing in recent years. It is beneficial to equip the electric load with a PE interface since it allows for more advanced control of the load performance. Furthermore, the increasing penetration of PE interfaced loads will bring both challenges and opportunities to power network resilience and reliability. However, the lack of modeling and control design for PE interfaced load units in the transmission-level power network analysis, especially for these high-penetrated high-power-rating load applications, limits the accuracy of evaluating the dynamic performance and stability status of the power network. Additionally, the complex configuration and high bandwidth dynamic performance of the PE interfaced load computationally prohibit the model development in transient stability (TS) simulation programs. Therefore, the dynamic PE interfaced load model can be characterized considering the following aspects: 1) Utilize the real-time experimental platform to represent the PE load dynamic performance since the power testbed can reflect the power grid operation with more robustness. 2) Adapt the simplified PE-based model to TS simulation tools, which focus on grid electromechanical transients and oscillations between 0.1 and 3 Hz. Research of the PE interfaced load towards its modeling and control design in different simulation environments and the flexible contribution to the grid operation has been conducted. First, the variable speed drive (VSD) based motor load is studied as a typical PE interfaced load, which can actively interact with power grid operation. The model of VSD load is introduced and applied to the power emulator for the multi-converter-based hardware testbed (HTB) in the Center of Ultra-wide-area Resilient Electric Energy Transmission Network (CURENT). Second, the aggregated performance of multiple VSD load units with grid frequency support function is characterized. Third, the fast electric vehicle (EV) charging unit is studied as a typical PE interfaced load with high power consumption. The generic model of EV charger load is developed based on the detailed switching model. The accuracy of the proposed EV charger load TS model has been verified by comparing it to simulation results of the equivalent electromagnetic (EMT) model

Design And Implementation Of Co-Operative Control Strategy For Hybrid AC/DC Microgrids

This thesis is mainly divided in two major sections: 1) Modelling and control of AC microgrid, DC microgrid, Hybrid AC/DC microgrid using distributed co-operative control, and 2) Development of a four bus laboratory prototype of an AC microgrid system. At first, a distributed cooperative control (DCC) for a DC microgrid considering the state-of-charge (SoC) of the batteries in a typical plug-in-electric-vehicle (PEV) is developed. In DC microgrids, this methodology is developed to assist the load sharing amongst the distributed generation units (DGs), according to their ratings with improved voltage regulation. Subsequently, a DCC based control algorithm for AC microgrid is also investigated to improve the performance of AC microgrid in terms of power sharing among the DGs, voltage regulation and frequency deviation. The results validate the advantages of the proposed methodology as compared to traditional droop control of AC microgrid. The DCC-based control methodology for AC microgrid and DC microgrid are further expanded to develop a DCC-based power management algorithm for hybrid AC/DC microgrid. The developed algorithm for hybrid microgrid controls the power flow through the interfacing converter (IC) between the AC and DC microgrids. This will facilitate the power sharing between the DGs according to their power ratings. Moreover, it enables the fixed scheduled power delivery at different operating conditions, while maintaining good voltage regulation and improved frequency profile. The second section provides a detailed explanation and step-by-step design and development of an AC/DC microgrid testbed. Controllers for the three-phase inverters are designed and tested on different generation units along with their corresponding inductor-capacitor-inductor (LCL) filters to eliminate the switching frequency harmonics. Electric power distribution line models are developed to form the microgrid network topology. Voltage and current sensors are placed in the proper positions to achieve a full visibility over the microgrid. A running average filter (RAF) based enhanced phase-locked-loop (EPLL) is designed and implemented to extract frequency and phase angle information. A PLL-based synchronizing scheme is also developed to synchronize the DGs to the microgrid. The developed laboratory prototype runs on dSpace platform for real time data acquisition, communication and controller implementation