Design and analysis of capacitive power transfer system for low power applications

Capacitive power transfer (CPT) system has been chosen as an alternative to perform the contactless power transfer in recent years. Advantages of CPT includes ability to confine electric field between coupling plates, power transfer capability through metal barriers, low eddy current power losses in metal surroundings, as well as the potential to minimise circuit size and costing. However, the challenge of handling CPT includes the separation distance between the transfer plates. This thesis focuses mainly on the development of a fundamental theory of CPT system and its application for low power contactless charging, starting from designing and analysing Class E resonant inverter to generating high frequency AC power source to drive the CPT system. The design is ensured to fulfil Zero-Voltage Switching (ZVS) condition in order to avoid switching loss. In electronic system, the quality factor, QL represents the effect of electrical resistance towards the system. By using Class E power amplifier circuit, the system with QL = 10 produced better results as compared to QL = 40. Considering the sensitivity of components variation, the investigation of Class E resonant inverter with π1a impedance matching circuit is done to act as a compensation network in order to enable efficient power transfer between the two parts of the system for wider load-range changes. The size of the capacitive plates was also succeeded to be reduced to half of the initial measurement by implementing the impedance matching network. The implementation of aluminium plate as transfer material for the CPT system shown the peak-to-peak value of output voltage is 25.5V with 52.55% duty cycle. After an impedance matching being inserted into the system, the experimental work produced 9.51W with 95.10% efficiency. Different materials of capacitive plates were also been investigated and discussed further in this thesis by providing the consequences of using particular materials towards the efficiency of the system. Copper has shown the best results by producing a better exponential decrease as compared to aluminium and zinc, in line graph of the output voltage

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Demonstration of a switchless Class E/Fodd dual-band power amplifier

A 250 W dual-band power amplifier belonging to the Class E/F switching amplifier family is presented. The amplifier operates in the 7 MHz and 10 MHz HAM bands, achieving 16 dB and 15 d B gain with power added efficiencies (PAE) of 92% and 87% in those bands, respectively. It utilizes dual-resonant passive input and output networks to achieve high-efficiency Class E/Fodd operation at both frequencies of operation, allowing the same passive networks to be used for both frequency bands without the use of band-select switches

A Power Efficient Audio Amplifier Combining Switching and Linear Techniques

Integrated Class D audio amplifiers are very power efficient, but require an external filter which prevents further integration. Also due to this filter, large feedback factors are hard to realise, so that the load influences the distortion- and transfer characteristics. The amplifier presented in this paper consists of a switching part that contains a much simpler filter, and a linear part that ensures a low distortion and flat frequency response. A 30W version was realised. The switching part of the amplifier was integrated in a BCD process. Together with a linear part and with a loudspeaker as load, it has a flat frequency response +/- 0.3dB, a dissipation that is up to 5 times lower than a traditional class AB audio amplifier, and a distortion of <0.02% over power and frequency range

A New Design of Capacitive Power Transfer Based on Hybrid Approach for Biomedical Implantable Device

This paper presents the development of a new design method of capacitive power transfer (CPT) which is based on hybrid concept for Biomedical Implants. This method is able to improve various issues found in the widely used CPT system that is bipolar CPT method. Based on the ability of this purposed, the simulation of the CPT system has been designed to prove an amount of power transferred through a layer of tissue. The design used to validate the suggested model which to powering implanted device, and it was performed with 3cm square plates, which have a layer of beef with the 5mm thickness in between 2 coupling plate. Power signal was generated by Class E zero voltage switching. The Class E zero voltage switching has been designed to generating alternate current with the 1MHz frequency appropriate to the hybrid CPT system specification.

Simulation-based Study of Capacitance Values Affected by Various Dielectric Materials and Distances for Low Power Wireless Power Transfer System

Capacitive Power Transfer (CPT) system is nowadays getting better attention by some of the researchers who are focusing on wireless power transfer field. This is because of the simplicity, small size, and better reaction towards EMI characteristics of the method. Furthermore, the efficiency of the CPT system is greatly influenced by the coupling capacitances which are varied by distances and permittivity values. Thus, this paper attempts to converge into the effect of several dielectric materials towards capacitance values and also the effect of the capacitive plates’ distances towards the output power. By using Class E circuit configuration and MATLAB Simulink as the simulation software, the results are then explained graphically. From those simulations, the work achieved 90.7% as highest efficiency as compared to the theoretical values

Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

Low power, compact charge coupled device signal processing system

A variety of charged coupled devices (CCDs) for performing programmable correlation for preprocessing environmental sensor data preparatory to its transmission to the ground were developed. A total of two separate ICs were developed and a third was evaluated. The first IC was a CCD chirp z transform IC capable of performing a 32 point DFT at frequencies to 1 MHz. All on chip circuitry operated as designed with the exception of the limited dynamic range caused by a fixed pattern noise due to interactions between the digital and analog circuits. The second IC developed was a 64 stage CCD analog/analog correlator for performing time domain correlation. Multiplier errors were found to be less than 1 percent at designed signal levels and less than 0.3 percent at the measured smaller levels. A prototype IC for performing time domain correlation was also evaluated