On the Reversible Effects of Bias-Stress Applied to Amorphous Indium-Gallium-Zinc-Oxide Thin Film Transistors

The role of amorphous IGZO (Indium Gallium Zinc Oxide) in Thin Film Transistors (TFT) has found its application in emerging display technologies such as active matrix liquid crystal display (LCD) and active matrix organic light-emitting diode (AMOLED) due to factors such as high mobility 10-20 cm2/(V.s), low subthreshold swing (~120mV/dec), overall material stability and ease of fabrication. However, prolonged application of gate bias on the TFT results in deterioration of I-V characteristics such as sub-threshold distortion and a distinct shift in threshold voltage. Both positive-bias and negative-bias affects have been investigated. In most cases positive-stress was found to have negligible influence on device characteristics, however a stress induced trap state was evident in certain cases. Negative stress demonstrated a pronounced influence by donor like interface traps, with significant transfer characteristics shift that was reversible over a period of time at room temperature. It was also found that the reversible mechanism to pre-stress conditions was accelerated when samples were subjected to cryogenic temperature (77 K). To improve device performance BG devices were subjected to extended anneals and encapsulated with ALD alumina. These devices were found to have excellent resistance to bias stress. Double gate devices that were subjected to extended anneals and alumina capping revealed similar results with better electrostatics compared to BG devices. The cause and effect of bias stress and its reversible mechanisms on IGZO TFTs has been studied and explained with supporting models

From Process to Circuits: New Perspectives to Solar Cell Design

As the demand for cheap and clean energy sources increased over the last two decades, solar cells have proven to be strong candidates against the fossil fuels. From an economic perspective, in order to replace fossil fuels, it is required to reduce the cost of solar cells. This can be achieved by depositing thinner absorber layers under low process temperatures, yet these efforts lead to poorer efficiency values. Addressing such trade-offs and providing solutions to this problem have been the main objectives of this study

AMOLED Displays with In-Pixel Photodetector

The focus of this chapter is to consider additional functionalities beyond the regular display function of an active matrix organic light-emitting diode (AMOLED) display. We will discuss how to improve the resolution of the array with OLED lithography pushing to AR/VR standards. Also, the chapter will give an insight into pixel design and layout with a strong focus on high resolution, enabling open areas in pixels for additional functionalities. An example of such additional functionalities would be to include a photodetector in pixel, requiring the need to include in-panel TFT readout at the peripherals of the full-display sensor array for applications such as finger and palmprint sensing

알칼리 금속 도핑과 절연체 엔지니어링을 통한 고성능 용액 공정 산화물 박막 트랜지스터 개발에 관한 연구

학위논문 (박사)-- 서울대학교 융합과학기술대학원 융합과학부, 2017. 8. 김연상.Solution-processed oxide semiconductors thin-film transistors (TFTs) with transparent, flexible properties and low-cost manufacturing have a great potential for future display requiring advanced performances such as high resolution and large scale as well as unique properties such as transparency and flexibility. However, there are several limitations for practical applications. Especially, a relatively low field-effect mobility compared with that of low temperature poly Si (LTPS) TFTs and high vacuum-processed oxide semiconductor TFTs is a critical issue. Accordingly, many studies have mainly focused on the development of solution-processed oxide semiconductor TFTs having a high field-effect mobility with various methods. However, their low field-effect mobility still remains a problem. Herein, I propose alkali metal doping and dielectric engineering for the increase of field-effect mobility in solution-processed oxide semiconductor TFTs. Through alkali metal doping, the field-effect mobility of solution-processed ZnSnxOy (ZTO) TFTs was increased 2 ∼ 3 times. Also, with the dielectric engineering, the field-effect mobility of the ZTO TFTs could be dramatically enhanced. Using various analyses with X-ray diffraction (XRD), high-resolution transmission electron microscopy (HRTEM), atomic force microscopy (AFM), X-ray photoemission spectroscopy (XPS), developed TFT model, and the like, the mechanism how field-effect mobility is increased by the alkali metal doping and the dielectric engineering has been investigated. These methods have good potential for the application of the solution-processed oxide semiconductor in future display technology.Chapter 1. Introduction 1 1.1 References 5 Chapter 2. Literature Review and Theories 7 2.1 Thin-film transistor 7 2.1.1 Concept of thin-film transistor 7 2.1.2 Operation and parameters of TFT 10 2.1.3 Structures of TFT and their properties 14 2.2 Oxide semiconductor for TFT 17 2.3 Solution-process for oxide semiconductor TFT 23 2.4 High mobility solution-processed oxide semiconductor TFT 26 2.4.1 The need of high mobility TFT 26 2.4.2 Trends and issues 29 2.4.3 Alkali metal doping 32 2.4.4 Dielectric engineering 34 2.5 References 35 Chapter 3. High Performance Amorphous Zinc Tin Oxide Thin-Film Transistor through Alkali Metal doping 38 3.1 Overview 38 3.2 Development of alkali metal doped ZTO TFTs and electrical properties 42 3.3 Analysis of chemical properties of alkali metal doped ZTO through XPS Analysis 49 3.4 The study for role of alkali metal doping based on analyses 51 3.5 The investigation of the role of alkali metal doping through UV-visible spectroscopy 57 3.6 Experimental details 63 3.7 References 66 Chapter 4. Dramatic Enhancement of Field-Effect Mobility in Oxide Semiconductor Thin-Film Transistor through Dielectric Engineering 69 4.1 Overview 69 4.2 Development of HCA dielectric layer for dramatically enhancing a field-effect mobility 72 4.3 Electrical characterization of ZTO TFTs on HCA 75 4.4. Electrical characterization of ZTO TFTs on a bilayer dielectric layer 90 4.5 Characterization of abnormal electrical behavior in ZTO TFTs on HCA 99 4.6 Analysis of structure and material characterization with ZTO and HCA 106 4.7 Role of Al atoms in interface between ZTO and HCA 123 4.8 Electrical transport model for ZTO TFTs on HCA 127 4.9 Experimental details 131 4.10 References 135 Chapter 5. Conclusion 138 초록(국문) 140Docto

플라즈마 화학 기상 증착법을 이용한 베리어 필름 합성과 디스플레이 응용

학위논문 (박사)-- 서울대학교 대학원 : 자연과학대학 화학부, 2019. 2. 홍병희.자발광형 디스플레이이며, 저전압 구동이 가능하고 얇은 두께로 제작이 가능하며 동작속도가 매우 빠를 뿐만 아니라 높은 해상도 구현이 가능한 OLED는 디스플레이에서 빠른 성장세를 보이고 있다. 최근 OLED의 가장 큰 관심 분야는 모바일용 디스플레이와 대면적 TV, 그리고 플렉시블 및 투명 디스플레이 구현이다. 디스플레이를 구동하기 위한 구동소자는 수동형(passive matrix)과 능동형(active matrix, AM)로 나뉘며, 수동형에 비하여 고화질, 낮은 소비 전력, 대형화에 유리한 능동형 디스플레이가 선호된다. 표시소자를 능동 구동하기 위해서는 각 화소마다 박막 트랜지스터(thin-film transistor, TFT)와 같은 스위칭 소자를 부착시켜야 한다. 능동형 구동소자의 경우 현재의 TFT-LCD나 AMOLED용 백플레인에 주로 사용되는 비정질 실리콘(a-Si), 저온 다결정 실리콘 (LTPS) 기술이 우선 개발되어 응용되고 있다. 최근에는 큰 밴드 갭을 가지는 비정질 산화물 반도체를 이용해 투명하면서 빠른 응답속도의 디스플레이 구동소자에 대한 연구가 활발히 진행되고 있다. 또한 배선의 RC Delay를 최소화 시켜야 하고, 파워소비량을 줄여야 하는 기술적인 문제가 있다. 디스플레이의 고해상도인 UHD (Ultra High Definition)의 backplane에서 고속 TFT 구현을 위하여 SD(Source-Drain) 메탈 배선 구현은 필수적인 요소이다. 본 연구에서는 SD 메탈 배선으로써 저저항 배선인 Copper 배선의 diffusion barrier 역할을 하는 Graphite 성장을 다루고 있다. 기존의 Graphene 합성은 기계적 및 화학적 박리 방법에는 대면적 패널 구현으로써 한계가 있다. 현재까지 대형 Size scale Graphene 시도는 전극으로써 Graphene 활용은 있지만, 이 구현은 Thermal CVD (900~1000℃)에서 Graphene 을 합성하고, Glass에 transfer 한 논문으로써 실제 대면적으로 만드는 공정 적용에는 한계가 있다. 이에 현재 많이 연구는 진행 중이고 있지만, PECVD (Plasma Enhanced Chemical Vapor Deposition)를 이용한 graphite 박막 합성은 대형 size, mass production을 가능하게 하며, 아직 mass production 적용을 위해 연구해야 할 점은 많지만, 저온 공정 Graphite 합성이 가능하다면, large scale device 구현에 한층 더 진보된 기술이 될 것임을 확신한다. 본 연구에서 Copper diffusion barrier 으로써의 역할을 검증하고, 증착 온도를 저온으로 합성함으로써 TEM 및 EDAX 분석으로 Graphite barrier 및 mass production의 가능성을 검증하였다. 본 연구의 직접적인 PECVD 합성 방법을 통해 대면적이 가능함을 제시함으로써 기존의 대면적 합성 문제점을 해결해 줄 수 있는 방안이 될 것이다. 또한 디스플레이의 TFT 특성도 기존의 Active material 인 a-Si TFT보다 훨씬 더 높은 고이동도 소자를 요구하며, 특히 투명 디스플레이의 적용 가능하며, 고이동도 특성을 균일하게 가질 수 있는 신규 TFT를 요구하게 되었다. 이에 대한 방안으로 산화물 TFT로써 ZnO (Zinc Oxide), IZO (Indium Zinc Oxide), a-IGZO (Amorphous Indium Gallium Zinc Oxide) 등의 재료가 연구되고 있다. 기존의 a-Si의 이동도 (<1cm2/V·S) 보다 높은 이동도를 가진 IGZO 재료는 투명한 소자로써 투명디스플레이에서도 활용이 가능하여, 응용성을 확대하고 있다. 본 연구에서는 투명디스플레이 에서도 활용이 가능하도록 a-IGZO를 substrate로 하는 Graphite 박막을 합성 방법을 제시하고, 대면적 구현으로써 그 응용성을 기대하고 있다. Graphite의 저온 합성 기술 개발은 기존 라인의 CVD 장비 교체 없이 단지 Graphene Gas 사용만으로 공정을 구현한다는 점이 cost 및 공정 단순화의 관점에서 많은 장점이 있다. 또한 고속 구동을 위하여 SD 배선으로 metal뿐 아니라 산화물 반도체로도 Graphite 합성의 catalyst로써 사용되어, 패널 구현을 가능하게 해준다는 관점에서 의미가 있다. 또한 Graphite 합성 기술을 thin film 박막을 만들어 다른 application 에서도 활용 가능함을 보여줌으로써 파급 효과가 크다고 판단된다. 다음 연구에서는 LCD 디스플레이에서 Backlight 사용이 필수적이다. Back light는 가시광선 영역 뿐 아니라 UV 파장영역도 포함하고 있으며, Active 재료인 a-IGZO 소자에서 TFT 특성의 불안정성의 문제를 가지고 있다. IGZO의 특성상 UV 파장대에서의 빛과의 반응으로 TFT 소자의 신뢰성 특성이 악화되는 문제점을 해결하고자 Barrier 박막을 사용이 필수적인 요소이다. 본 연구에서는 TFT의 신뢰성 및 안정성을 유지하기 위해서 Photo blocking barrier로써 SiGe (Silicon Germanium) 박막 재료 합성을 통하여 TFT 신뢰성의 특성 변화 없는 것을 연구하였다. 이전 SiGe 연구되어진 바로는 태양전지에서 P-I(intrinsic layer)-N형 구조에서 중간 삽입층에서 불순물이 첨가되지 않은 무첨가층 (Intrinsic layer)에서 SiGe 이 광흡수층으로 사용되어진 연구가 있었다. 본 연구에서는 TFT 소자에서 a-IGZO 가 광반응으로 인해 산소 결핍 (Oxygen Vacancy)을 막아 TFT 특성의 저하 효과를 막고자 SiGe의 광 차단 박막 형성을 통해 광반응으로 인한a-IGZO특성 변화가 되지 않도록 하였다. 또한 박막 형성 및 적층 구조에서 SiGe 와 IGZO의 박막 사이에 Capacitance 형성으로 전자의 charge가 IGZO 박막 계면에 누적되어, 트랜지스터 특성이 단락(short) 현상이 발생 하였으며, 이를 방지하기 위해 Buffer layer 의 두께 조절이 중요하였다. 이에 Buffer layer의 두께 최적화를 통해 하부에서 들어오는 빛에도 차단을 할 수 있는 Barrier 적층 구조를 만들어 TFT 소자의 신뢰성 개선됨을 보여주고자 하였다. 스마트 Window 및 냉장고에서 문을 열지 않고 내용물을 확인할 수 있는 투명 디스플레이 및 플렉시블 디스플레이 구현을 위해 여러 요소의 기술 연구가 진행되고 있으며, 이 구현을 위해 본 연구의 Barrier 박막 구현은 필수적인 요소로 응용성이 확대되어 활용됨을 기대해 본다.OLED is a self-emissive display can be driven at low voltage and manufactured in a thin layer. In addition, this display operates at a very high speed and emit a color that can be rapidly implemented. Recently, OLEDs main interest is mobile screen, large screen TV, flexible and transparent display. The driving device for display is classified to the passive matrix and active matrix. Active matrix is preferred because of higher resolution, lower energy consumption, and large size screen. To apply active matrix on display device, a switching device such as thin-film transistor (TFT) is attached to each pixel. For active driving devices, amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS) technologies are applied in current TFT –LCD or AMOLED back frame. Recently, there is an ongoing research on using amorphous oxide semiconductors with large bandgaps to research transparent and fast responsive display driving devices. Moreover, RC delay has a technical problem that must be minimized and reduce power consumption. Implementation of Source Drain (SD) is a metal wiring essential element for high-speed TFT execution in high-resolution UHD (Ultra High Definition) displays backplane. In this study, the graphite growth plays the role of diffusion barrier of copper wiring that has low resistance wiring with SD metal wiring. The chemical and mechanical stripping methods of conventional graphene synthesis application on large area panels is limited. Up to now, the large size graphene has been used as an electrode, but this implementation is limited to making the large-scale process by synthesizing graphene at thermal CVD (900~1000°C) and transferring it to the glass. Despite the fact, a lot of ongoing studies, graphites thin film synthesis using Plasma Enhanced Chemical Vapor Deposition (PECVD) enables large size and mass production. Furthermore, this area still requires more research on mass production. If low-temperature process for graphite synthesis is possible, this will become a more advanced technology for device implementation. In this study, the role of copper diffusion barrier was verified, and the possibility of graphite barrier and mass production was verified by TEM and EDAX analysis by synthesizing the deposition temperature at low temperature. In addition, this study suggests the large size display can be obtained through direct PECVD synthesis that will solve the existing problems of large size synthesis. The displays TFT characteristics also require a high mobility device that is much higher than the conventional active material a-Si TFT. In particular, a new TFT capable of applying a transparent display and uniformly having high mobility characteristics is required. Materials such as ZnO (Zinc Oxide), IZO (Indium Zinc Oxide) and IGZO (Indium Gallium Zinc Oxide) have been studied as oxide TFTs. IGZO materials with higher mobility than conventional a-Si mobility (<1 cm2 / V · s) are transparent devices and can be used in transparent displays, thus extending applicability. In this study, we propose a graphite synthesis based on IGZO to be applicable to transparent display and expect the application on large size displays. The low-temperature Graphite synthesis has many advantages in terms of cost and process simplification because it implements the process only by using Graphene gas without replacing existing CVD equipment. In addition, it can be used as a graphite synthesis catalyst not only for metal but also for the oxide semiconductor, to raise activation. Moreover, the graphite synthesis to make a thin film can be applied to other fields. In the next study, it is essential to use backlight in LCD display. The backlight not only includes the visible light but also the UV region, and has instability of TFT characteristics in the active material IGZO device. Due to IGZOs reaction to light in UV region, it is essential to use a barrier film in order to solve the reliability characteristics of the TFT device deterioration. To maintain the reliability and stability of the TFT, this study on reliability of the TFT was not changed by SiGe (Silicon Germanium) synthesis thin film as a photo blocking barrier. Based on previous research on SiGe has been used as the light absorbing layer in the intrinsic layer in which a P-I (intrinsic layer)-N type structure in a solar cell that is not doped with an impurity in an intermediate insertion layer. In this study, in order to prevent oxygen vacancy during a-IGZO photoreaction on TFT device, the formation of a light-shielding film of Si-Ge prevents oxygen deficiency. Capacitance formation between SiGe and IGZO thin film in the thin film formation and lamination structure accumulates electrons charge on the IGZO thin film interface. The characteristics of the transistor were short, and to prevent this shortness, it is important to control the thickness of the buffer layer. Therefore, this shows that the reliability of the TFT device is improved by making the barrier laminate structure that can block the light from the bottom through the optimization of the thickness of the buffer layer. There are various ongoing technological studies on transparent and flexible displays that to observe the contents without opening the door through the smart window and refrigerator. For this application, the thin film barrier is an essential element and expect to be implemented.Table of Contents Abstract.........................................................................1 Contents........................................................................6 List of Figures.................................................................9 List of Tables................................................................15 Chapter 1. Introduction................................................16 1.1. Graphene characteristics 1.2. Amorphous Si:H and LTPS TFT backplane technology in display 1.3. High performance amorphous In-Ga-Zn-O TFTs 1.4. Overview of PECVD system 1.5. References Chapter 2. Growth of thin graphite films for solid diffusion barriers .......................................................60 2.1. Large-scale transfer-free growth of thin graphite films at low temperature for solid diffusion barriers 2.1.1. Introduction 2.1.2. Experimental 2.1.3. Results and discussion 2.1.4. Conclusion 2.1.5. References Chapter 3. Growth of silicon germanium films for photo-blocking layers in industrial display.................99 3.1. Silicon germanium photo-blocking layers for a-IGZO based industrial display 3.1.1. Introduction 3.1.2. Experimental 3.1.3. Results and Discussion 3.1.4. Conclusion 3.1.5. References Abstract in Korean………………………………………130 Appendix……………………………………………………135Docto

Thermal & electrical simulation for the development of solid-phase polycrystalline silicon TFTs

Solid phase crystallization (SPC) is a processing technique used for conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si). SPC can potentially be used as an alternative to excimer laser annealing to fabricate the semiconductor layer for thin-film transistors (TFTs) in active-matrix liquid crystal display (AMLCD). It is a technique suitable for large-area applications since it involves easily scalable thermal processes in the form of rapid thermal annealing (RTA) and furnace annealing (FA). The SPC parameter space involves the time and temperature of the FA, and the time, temperature, and number of pulses in the RTA process. In developing new process flows for thin-film transistors (TFTs) using SPC, thermal and electrical device simulation are invaluable tools. Comsol® was utilized to explore this SPC experimental parameter space, and provided important insight on temperature conditions not directly measureable on glass substrates (see Fig. 1). Silvaco\u27s Atlas® was utilized to evaluate the TFT response variables of sub-threshold slope (SS), threshold voltage (VT), and maximum current (Imax). Further, a procedure for fitting TFT device characteristics using Atlas was developed. From this simulation fit (see Fig. 2), theoretical trap state distributions for the semiconducting film can be extracted, as well as the trap state distributions at the oxide-semiconductor interfaces

GaN Micro-LED Integration with Thin-Film Transistors for Flexible Displays

The research presented provides a systematic attempt to address the major challenges for the development of flexible micro-light-emitting diode (LED) displays. The feasibility of driving GaN-based micro-LEDs with a-Si:H-based thin-film transistors by using a thin-film bonding and transfer process was initially proposed. This approach was implemented to create an inverted pixel structure where the cathode of the LED is connected directly to the drain contact of the drive TFT resulting in a pixel circuit having more than 2× higher brightness compared to a standard pixel design. This “paste-and-cut” technique was further demonstrated for the development of flexible displays, enabling the study of the effect of mechanical strain and self-heating of the devices on plastic. Through a finite-element analysis, it was determined that the applied stress-induced strain near the quantum wells of the micro-LEDs are negligible for devices with diameters smaller than 20 microns. Thermal simulation of the LEDs on plastic revealed that a copper bond layer thicker than 600 nm can be used to alleviate self-heating effects of the micro-LEDs. Using these design parameters, micro-LED arrays with 20 micron diameter were integrated onto flexible substrates to validate the theoretical predictions. Further scaling of the LED size revealed substrate bending also tilts the direction of the LED structure, allowing further extraction of light. This effect was demonstrated using nanowire LEDs with a 250 nm diameter transferred onto plastic, where the light output could be enhanced by 2× through substrate bending. Finally, through the removal of bulk defect and surface states, fabrication of highly efficient micro-LEDs having > 400% increase in light output (compared to conventional diodes) was achieved. This outcome was accomplished through the removal of the defective buffer region adjacent to the active layers of the LED and minimization of the non-radiative recombination at the sidewalls. The former was accomplished through the removal of the buffer layer after separation of the LED from the process wafer while the latter is accomplished using a surround cathode gate electrode to deplete free carriers from the sidewall of the forward-biased LED. The resulting performance enhancements provided a basis for high-brightness flexible micro-LED displays developed in this dissertation

Implant Activated Source/Drain Regions for Self-Aligned IGZO TFT

In this work, amorphous Indium Gallium Zinc Oxide (IGZO) TFTs with channel lengths scaled as small as L = 1 µm are presented which demonstrate excellent electrical characteristics, however the traditional metal-contact defined source/drain regions typically require several microns of gate overlap in order to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. In addition, further scaling the channel length by simply reducing the source/drain metal gap is not feasible. The focus of this study is to investigate techniques to realize self-aligned (SA) IGZO TFTs that are not subject to gate-source/drain misalignment due to overlay error or process bias. Top gate (TG) co-planar and bottom gate (BG) staggered TFTs are fabricated using plasma immersion and ion implantation to selectively form conductive IGZO regions, with the channel region blocked by a gate-defined mask. Among the investigated treatments, oxygen plasma activation and ion implanted activation via 11B+ and 40Ar+ has been successfully demonstrated. Due to metal gate charging during ion implantation of SA-TG devices, the characteristics show a significant left-shift whereas SA-BG devices do not show this behavior. Electrical results suggest a defect-induced mechanism is involved with 40Ar+ implant activation of the S/D regions. However, 11B+ implant activation is attributed to the formation of an electrically active donor species involving chemical bonding. Both boron and argon demonstrate pronounced degradation in charge injection at higher dose treatments. Finally, a novel lithographic strategy which utilizes top-side flood exposure rather than a back-side through-glass exposure has also been explored, which would enable SA-BG devices on non-transparent substrates

Interpretation and Physical Modeling of Electronic Transport and Defect States in IGZO Thin-Film Transistors

This work is a comprehensive study on the interpretation and modeling of electronic transport behavior and defect states in indium-gallium-zinc-oxide (IGZO) TFTs. Key studies have focused on advancing the state of IGZO TFTs by addressing several challenges in device stability, scaling, and device modeling. These studies have provided new insight on the associated mechanisms and have resulted in the realization of scaled thin-film transistors that exhibit excellent electrical performance and stability. This work has demonstrated the ability to scale the conventional inverted staggered IGZO TFT down to one micron channel length, with excellent on-state and off-state performance where the VT ≈1 V, µeff =12 cm2/Vs, Ileak ≤ 10-12 A/µm and SS ≈ 160 mV/dec. The working source/drain electrodes are direct metal contact regions to the IGZO, which requires several microns of gate overlap to provide ohmic behavior with minimal series resistance and ensure tolerance to overlay error. New results utilizing ion implantation for self-aligned source/drain regions present a path towards submicron channel length. This strategy offers a reduction in channel length as well as parasitic capacitance, which translates to improvement in RC delay and associated voltage losses due to charge-sharing. The realization of self-aligned TFTs using boron ion implantation for selective activation was introduced in a first-time report of boron-doped IGZO. Cryogenic measurements made on long-channel devices has revealed temperature-dependent behavior that is not explained by existing TCAD models employed for defect states and carrier mobility. A completely new device model using Silvaco Atlas has been established which properly accounts for the role of donor-like oxygen vacancy defects, acceptor-like band-tail states, acceptor-like interface traps, and a temperature-dependent intrinsic channel mobility. The developed model demonstrates a remarkable match to transfer characteristics measured at T = 150 K to room temperature. A power-law fit for the µch = f(T) relationship, which resembles 〖μ ~ T〗^((+3)⁄2) behavior consistent with ionized defect scattering. The mobility model is expressly independent of carrier concentration, without dependence on the applied gate bias. The device model is consistent with a compact model developed for circuit simulation (SPICE) that has been recently refined to include on-state and off-state operation. While IGZO is the only AOS technology mature enough for commercialization, the effective electron channel mobility µeff ~ 10 cm2/Vs presents a performance limitation. Other candidate AOS materials which have higher reported channel mobility values have also been investigated; specifically, indium-tungsten-oxide (IWO) and indium-gallium-tin-oxide (ITGO). These investigations serve as preliminary studies; device characteristics support the claims of high channel mobility; however the influence of defect states clearly indicates the need for further process development. The advancements realized in IGZO TFTs in this work will serve as a foundation for these alternative AOS materials

전류 센싱 피드백 시스템을 이용한 고안정성 산화물 TFT 쉬프트 레지스터의 설계 및 제작

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2017. 2. 정덕균.Integration of shift registers on the glass panel allows the display to be thinner, lighter, and cheaper to produce, thanks to the reduction of the number of ICs for scanning horizontal lines. Circuits of the shift register employing n-type thin film transistors (TFTs), such as hydrogenated amorphous silicon (a-Si:H) and oxide TFTs, have been reported. Recently, oxide TFTs attract much attention due to their high mobility (5~10 cm2/V∙s) compared with that of a-Si:H TFT (0.8cm2/V∙s). However, oxide TFTs often suffer from severe degradation of the threshold voltage (VTH) against the temperature and electrical stress. In this paper, in order to compensate the instability of oxide TFTs in the shift register, an oxide TFT with double gates, which can control VTH by varying the top gate bias (VTG) is adopted. The top gate of the double-gate TFT can be fabricated in the same process for the pixel IZO (Indium Zinc Oxide) so that an additional process only for the top gate is not required. Adequate VTG is provided timely, adaptively to the gate of the oxide TFTs to stabilize the threshold voltage. The fabrication result shows that the proposed shift register using VTG set at an adapted value become stable at 100℃ whereas the conventional one is mal-functioning. The optimum VTG varies from product to product and changes continuously over the lifetime of the display. Therefore, the feedback driving system suitable for the proposed shift register is required to search the optimum VTG. The system has two main functionsthe first is to sense the current of shift register and the second is the searching algorithm for finding the optimum VTG. When the transistors are degraded by an external stress, the current of the whole shift registers is changed. The information about the VTH degradation in the shift register can be gathered via current sensing circuit. The sensed current is integrated to generate the output and is forwarded to an ADC. The binary-converted current of shift register is processed by the proposed algorithm in the digital domain for obtaining an optimum VTG and then the result is converted back to analog to generate VTG. The IC implementing such functions is fabricated in a 0.18 μm BCDMOS process. When the shift register current is measured on the conventional system with increasing temperature up to 80℃, it is increased to more than 10 times than that at the room temperature. However, the proposed feedback system keeps a highly stable (<13%) current level of shift register up to 80℃ with an optimized VTG.Abstracts i Table of Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 Background 2 1.2 Outline 7 Chapter 2 Review of oxide-based TFT device and N-type TFT circuit design 8 2.1 Overview 9 2.1.1 Characteristics of Oxide TFT 9 2.2 Oxide-based TFT 14 2.2.1 Electrical characteristics of oxide-based TFT 14 2.2.2 Stability of oxide-based TFT 18 2.3 NMOS driving circuit 24 2.3.1 Bootstrapping driving circuit 24 2.3.2 Shift register with n-type TFT 28 Chapter 3 Proposed Oxide TFT Shift Register 37 3.1 Overview 38 3.2 Characteristic of Double Gate TFT 39 3.3 Design of New shift register 46 3.3.1 Simulation Result of Conventional shift register 46 3.3.2 New shift register using Double Gate TFT 51 3.3.3 Simulation Modeling of Double Gate TFT 58 3.3.4 Simulation and Experimental Result 61 Chapter 4 Real Time Current-Sensing Feedback Compensation System 71 4.1 Overview 72 4.2 System Architecture 74 4.3 Circuit Design 77 4.3.1 Current Sensing Block 77 4.3.2 ADC/DAC Block 85 4.4 Optimum Point Searching Algorithm 100 4.5 System Verification 106 Chapter 5 Summary 116 Appendix A SPICE models 118 Bibliography 120Docto