Experimental Verification of a Harmonic-Rejection Mixing Concept using Blind Interference Canceling

Abstract—This paper presents the first practical experiments\ud on a harmonic rejection downconverter, which offers up to 75 dB of harmonic rejection, without an RF filter. The downconverter uses a two-stage approach; the first stage is an analog multipath/ multi-phase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation and to find practical performance limitations. Measurement results show that the harmonic rejection of the downconverter is insensitive to frontend nonlinearities and LO phase noise. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must\ud be designed to provide as much attenuation of the desired signal as possible

A Blind Interference Canceling Technique for Two-Stage Harmonic Rejection in Down-mixers

This paper presents practical experiments on a harmonic rejection down-mixer, which offers up to 75 dB of harmonic rejection, without an RF filter. The down-mixer uses a two-stage approach; the first stage is an analog multi-path/multiphase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must be designed to provide as much attenuation of the desired signal as possible. Front-end nonlinearities and DC offsets are discussed

A CMOS spectrum analyzer frontend for cognitive radio achieving +25dBm IIP3 and −169 dBm/Hz DANL

A dual RF-receiver preceded by discrete-step attenuators is implemented in 65nm CMOS and operates from 0.3– 1.0 GHz. The noise of the receivers is reduced by cross-correlating the two receiver outputs in the digital baseband, allowing attenuation of the RF input signal to increase linearity. With this technique a displayed average noise level below -169 dBm/Hz is obtained with +25 dBm IIP3, giving a spurious-free dynamic range of 89 dB in 1 MHz resolution bandwidth

A Two-stage approach to harmonic rejection mixing using blind interference cancelling

Current analog harmonic rejection mixers typically provide 30–40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30–45 dB

X-Band Front-end Module of FMCW RADAR for Collision Avoidance Application

A frequency modulated continuous wave (FMCW) radar front-end module is developed as a laboratory prototype of NECTEC, NSTDA. The performance of proposed prototype is verified by the reflection test of aluminum plates in outdoor environment. The frequency domain data from a spectrum analyzer was measured at every 20 meters of the distance between the front-end prototype and the aluminum plate until the maximum distance of 200 meters is reached. The calculation of the beat frequencies at different range of reflecting aluminum plates is presented. The maximum error between measured and calculated distances does not exceed 5.02 percent. The effect of different radar cross section (RCS) of reflecting objects of 0.3, 0.8 and 1.5 m2 plate area are analyzed. The low value of different received power ratio per one squared meter unit area of 0.66 percent is obtained to prove the consistency of reflected power level over the different size of object under test.

Design of RF Frontend Unit to Avoid Intermodulation Using Arduino Uno

Designing a Radio Frequency (RF) front end is vastly realized for determining the level of integration that is required in the signal chain inside the receivers to be idealistic. The receivers is susceptible to harmful intermodulation due to nonlinear RF front ends. In this paper, intermodulation distortion is avoided by a selective prototype hardware design of RF fort end which is connected with the Arduino Uno for controlling the power levels. The measurements are tested out as a result of injecting a signals within x-band frequencies and chosen different power levels are assumed. These measurements is revealed an accepted results for the intermodulation avoidance

Widely Tunable RF Frontend for the Universal Software Radio Peripheral: the MMP9000

This report presents the design and construction of a wideband transceiver in the context of an RF frontend for a software radio development platform, the Universal Software Radio Peripheral (USRP). This daughterboard is designed to operate at either full or half duplex modes over a frequency range of 100 MHz to 1.3 GHz or greater. It is fully integrated with both the USRP and GNU Radio, a free software radio development toolkit, to fully control the daughterboard via software

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

Radio over fiber enabling PON fronthaul in a two-tiered cloud

Avec l’avènement des objets connectés, la bande passante nécessaire dépasse la capacité des interconnections électriques et interface sans fils dans les réseaux d’accès mais aussi dans les réseaux coeurs. Des systèmes photoniques haute capacité situés dans les réseaux d’accès utilisant la technologie radio sur fibre systèmes ont été proposés comme solution dans les réseaux sans fil de 5e générations. Afin de maximiser l’utilisation des ressources des serveurs et des ressources réseau, le cloud computing et des services de stockage sont en cours de déploiement. De cette manière, les ressources centralisées pourraient être diffusées de façon dynamique comme l’utilisateur final le souhaite. Chaque échange nécessitant une synchronisation entre le serveur et son infrastructure, une couche physique optique permet au cloud de supporter la virtualisation des réseaux et de les définir de façon logicielle. Les amplificateurs à semi-conducteurs réflectifs (RSOA) sont une technologie clé au niveau des ONU(unité de communications optiques) dans les réseaux d’accès passif (PON) à fibres. Nous examinons ici la possibilité d’utiliser un RSOA et la technologie radio sur fibre pour transporter des signaux sans fil ainsi qu’un signal numérique sur un PON. La radio sur fibres peut être facilement réalisée grâce à l’insensibilité a la longueur d’onde du RSOA. Le choix de la longueur d’onde pour la couche physique est cependant choisi dans les couches 2/3 du modèle OSI. Les interactions entre la couche physique et la commutation de réseaux peuvent être faites par l’ajout d’un contrôleur SDN pour inclure des gestionnaires de couches optiques. La virtualisation réseau pourrait ainsi bénéficier d’une couche optique flexible grâce des ressources réseau dynamique et adaptée. Dans ce mémoire, nous étudions un système disposant d’une couche physique optique basé sur un RSOA. Celle-ci nous permet de façon simultanée un envoi de signaux sans fil et le transport de signaux numérique au format modulation tout ou rien (OOK) dans un système WDM(multiplexage en longueur d’onde)-PON. Le RSOA a été caractérisé pour montrer sa capacité à gérer une plage dynamique élevée du signal sans fil analogique. Ensuite, les signaux RF et IF du système de fibres sont comparés avec ses avantages et ses inconvénients. Finalement, nous réalisons de façon expérimentale une liaison point à point WDM utilisant la transmission en duplex intégral d’un signal wifi analogique ainsi qu’un signal descendant au format OOK. En introduisant deux mélangeurs RF dans la liaison montante, nous avons résolu le problème d’incompatibilité avec le système sans fil basé sur le TDD (multiplexage en temps duplexé).With the advent of IoT (internet of things) bandwidth requirements triggered by aggregated wireless connections have exceeded the fundamental limitation of copper and microwave based wireless backhaul and fronthaul networks. High capacity photonic fronthaul systems employing radio over fiber technology has been proposed as the ultimate solution for 5G wireless system. To maximize utilization of server and network resources, cloud computing and storage based services are being deployed. In this manner, centralized resources could be dynamically streamed to the end user as requested. Since on demand resource provision requires the orchestration between the server and network infrastructure, a smart photonic (physical layer)PHY enabled cloud is foreseen to support network virtualization and software defined network. RSOAs (Reflective Semiconductor Optical Amplifier) are being investigated as key enablers of the colorless ONU(Optical Network Unit) solution in PON (Passive Optical Network). We examine the use of an RSOA in radio over fiber systems to transport wireless signals over a PON simultaneously with digital data. Radio over fiber systems with flexible wavelength allocation could be achieved thanks to the colorless operation of the RSOA and wavelength reuse technique. The wavelength flexibility in optical PHY are inline with the paradigm of software defined network (SDN) in OSI layer 2/3. The orchestration between optical PHY and network switching fabric could be realized by extending the SDN controller to include optical layer handlers. Network virtualization could also benefit from the flexible optical PHY through dynamic and tailored optical network resource provision. In this thesis, we investigate an optical PHY system based on RSOA enabling both analog wireless signal and digital On-Off Keying (OOK) transportation within WDM (Wavelength Division Multiplexing) PON architecture. The RSOA has been characterized to show its potential ability to handle high dynamic range analog wireless signal. Then the RF and IF radio over fiber scheme is compared with its pros and cons. Finally we perform the experiment to shown a point to point WDM link with full duplex transmission of analog WiFi signal with downlink OOK signal. By introducing two RF mixer in the uplink, we have solved the incompatible problem with TDD (Time Division Duplex) based wireless system

Power-efficient Circuit Architectures for Receivers Leveraging Nanoscale CMOS

Cellular and mobile communication markets, together with CMOS technology scaling, have made complex systems-on-chip integrated circuits (ICs) ubiquitous. Moving towards the internet of things that aims to extend this further requires ultra-low power and efficient radio communication that continues to take advantage of nanoscale CMOS processes. At the heart of this lie orthogonal challenges in both system and circuit architectures of current day technology. By enabling transceivers at center frequencies ranging in several tens of GHz, modern CMOS processes support bandwidths of up to several GHz. However, conventional narrowband architectures cannot directly translate or trade-off these speeds to lower power consumption. Pulse-radio UWB (PR-UWB), a fundamentally different system of communication enables this trade-off by bit-level duty-cycling i.e., power-gating and has emerged as an alternative to conventional narrowband systems to achieve better energy efficiency. However, system-level challenges in the implementation of transceiver synchronization and duty-cycling have remained an open challenge to realize the ultra-low power numbers that PR-UWB promises. Orthogonally, as CMOS scaling continues, approaching 28nm and 14nm in production digital processes, the key transistor characteristics have rapidly changed. Changes in supply voltage, intrinsic gain and switching speeds have rendered conventional analog circuit design techniques obsolete, since they do not scale well with the digital backend engines that dictate scaling. Consequently, circuit architectures that employ time-domain processing and leverage the faster switching speeds have become attractive. However, they are fundamentally limited by their inability to support linear domain-to-domain conversion and hence, have remained un-suited to high-performance applications. Addressing these requirements in different dimensions, two pulse-radio UWB receiver and a continuous-time filter silicon prototypes are presented in this work. The receiver prototypes focus on system level innovation while the filter serves as a demonstration vehicle for novel circuit architectures developed in this work. The PR-UWB receiver prototypes are implemented in a 65nm LP CMOS technology and are fully integrated solutions. The first receiver prototype is a compact UWB receiver front end operating at 4.85GHz that is aggressively duty-cycled. It occupies an active area of only 0.4 mm², thanks to the use of few inductors and RF G_m-C filters and incorporates an automatic-threshold-recovery-based demodulator for digitization. The prototype achieves a sensitivity of -88dBm at a data rate of 1Mbps (for a BER of 10^-3), while achieving the lowest energy consumption gradient (dP/df_data=450pJ/bit) amongst other receivers operating in the lower UWB band, for the same sensitivity. However, this prototype is limited by idle-time power consumption (e.g., bias) and lacks synchronization capability. A fully self-duty-cycled and synchronized UWB pulse-radio receiver SoC targeted at low-data-rate communication is presented as the second prototype. The proposed architecture builds on the automatic-threshold-recovery-based demodulator to achieve synchronization using an all-digital clock and data recovery loop. The SoC synchronizes with the incoming pulse stream from the transmitter and duty-cycles itself. The SoC prototype achieves a -79.5dBm, 1Mbps-normalized sensitivity for a >5X improvement over the state of the art in power consumption (375pJ/bit), thanks to aggressive signal path and bias circuit duty-cycling. The SoC is fully integrated to achieve RF-in to bit-out operation and can interface with off-chip, low speed digital components. Finally, switched-mode signal processing, a signal processing paradigm that enables the design of highly linear, power-efficient feedback amplifiers is presented. A 0.6V continuous-time filter prototype that demonstrates the advantages of this technique is presented in a 65nm GP CMOS process. The filter draws 26.2mW from the supply while operating at a full-scale that is 73% of the V_dd, a bandwidth of 70MHz and a peak signal-to-noise-and-distortion ratio (SNDR) of 55.8dB. This represents a 2-fold improvement in full-scale and a 10-fold improvement in the bandwidth over state-of-the-art filter implementations, while demonstrating excellent linearity and signal-to-noise ratio. To sum up, innovations spanning both system and circuit architectures that leverage the speeds of nanoscale CMOS processes to enable power-efficient solutions to next-generation wireless receivers are presented in this work