1,231 research outputs found

    A Modular Programmable CMOS Analog Fuzzy Controller Chip

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    We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The architecture realizes a lattice partition of the universe of discourse, which at the hardware level means that the fuzzy labels associated to every input (realized by the label blocks) are shared among the rule blocks. This reduces the area and power consumption and is the key point for chip modularity. The proposed architecture is demonstrated through a 16-rule two input CMOS 1-μm prototype which features an operation speed of 2.5 Mflips (2.5×10^6 fuzzy inferences per second) with 8.6 mW power consumption. Core area occupation of this prototype is of only 1.6 mm 2 including the digital control and memory circuitry used for programmability. Because of the architecture modularity the number of inputs and rules can be increased with any hardly design effort.This work was supported in part by the Spanish C.I.C.Y.T under Contract TIC96-1392-C02- 02 (SIVA)

    Neuro-fuzzy chip to handle complex tasks with analog performance

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    This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input–output delay, and precision, performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 um standard technology. It has two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided

    Neuro-fuzzy chip to handle complex tasks with analog performance

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    This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, input-output delay and precision performs as a fully analog implementation. However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core [1]. Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture are smaller than those of its purely analog counterparts simply because most rules are implemented through programming. The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype. This prototype, called MFCON, has been realized in a CMOS 0.7μm standard technology. It has two inputs, implements 64 rules and features 500ns of input to output delay with 16mW of power consumption. Results from the chip in a control application with a DC motor are also provided

    CMOS design of adaptive fuzzy ASICs using mixed-signal circuits

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    Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level - prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5 /spl mu/m single-poly technology

    A 16 [email protected] Mixed-Signal Programmable Fuzzy Controller CMOS-1μm Chip

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    We present a fuzzy inference chip capable to evaluate 16 programmable rules at a speed of 2.5Mflips (2.5 × 10 6 fuzzy inferences per second) with 8.6mW power consumption. It occupies 2.89mm 2 (including pads) in a CMOS 1μm single-poly technology. Measurements are given to demonstrate its performance. All the operations needed for fuzzy inference are realized on-chip using analog circuitry compatible with standard VLSI CMOS technologies. On-chip digital control and memory circuitry is also incorporated for programmability. The chip architecture and circuitry are based on our design methodology for neurofuzzy systems reported in [1]. A few architectural modifications are made to share circuitry among rules and, thus, obtain reduced area and power consumption. The chip parameters can be learned in situ, for operation in a changing environment, by using dedicated hardware-compatible learning algorithms [1][8

    Modular Design of Adaptive Analog CMOS Fuzzy Controller Chips

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    Analog circuits are natural candidates to design fuzzy chips with optimum speed/power figures for precision up to about 1%. This paper presents a methodology and circuit blocks to realize fuzzy controllers in the form of analog CMOS chips. These chips can be made to adapt their function through electrical control. The proposed design methodology emphasizes modularity and simplicity at the circuit level -- prerequisites to increasing processor complexity and operation speed. The paper include measurements from a silicon prototype of a fuzzy controller chip in CMOS 1.5μm single-poly technology

    Intelligent fuzzy controller for event-driven real time systems

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    Most of the known linguistic models are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show a model for synchronous finite state machines based on fuzzy logic. Such finite state machines can be used to build both event-driven, time-varying, rule-based systems and the control unit section of a fuzzy logic computer. The architecture of a pipelined intelligent fuzzy controller is presented, and the linguistic model is represented by an overall fuzzy relation stored in a single rule memory. A VLSI integrated circuit implementation of the fuzzy controller is suggested. At a clock rate of 30 MHz, the controller can perform 3 MFLIPS on multi-dimensional fuzzy data

    Using Building Blocks to Design Analog Neuro-Fuzzy Controllers

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    We present a parallel architecture for fuzzy controllers and a methodology for their realization as analog CMOS chips for low- and medium-precision applications. These chips can be made to learn through the adaptation of electrically controllable parameters guided by a dedicated hardware-compatible learning algorithm. Our designs emphasize simplicity at the circuit level—a prerequisite for increasing processor complexity and operation speed. Examples include a three-input, four-rule controller chip in 1.5-μm CMOS, single-poly, double-metal technology

    Multiplexing architecture for mixed-signal CMOS fuzzy controllers

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    Limited precision imposes limits on the complexity of analogue circuits, and hence fuzzy analogue controllers are usually oriented to fast low-power systems with low-medium complexity. A strategy to preserve most of the advantages of an analogue implementation, while allowing a marked increment in system complexity, is presented.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0

    A modular CMOS analog fuzzy controller

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    The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy chips with optimum speed/power figures. This paper presents a sixteen rules-two inputs analog fuzzy controller in a CMOS 1 /spl mu/m single-poly technology based on building blocks implementations previously proposed by the authors (1995). However, such building blocks are rearranged here to get a highly modular architecture organized from two high level blocks: the label block and the rule block. In addition, sharing of membership function circuits allows a compact design with low area and power consumption and its highly modular architecture will permit to increase the number of inputs and rules in future chips with hardly design effort. The paper includes measurements from a silicon prototype of the controller
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