Design of an IDM-based determinant computing unit for a 130nm low power CMOS ASIC acoustic localization processor

https://www.scopus.com/inward/record.url?eid=2-s2.0-84945151182&partnerID=40&md5=6ddf5c2778c6b512bf6531ff81a9fd36A determinant computing circuit in floating point format has been designed and tested for use in a CMOS ASIC acoustic localization processor. The Internal Division Method (IDM) was used to implement the operation, employing a modified SRT radix-4 circuit for division operations. The unit was designed for VLSI implementation in a commercial 130nm low-power CMOS process, with an operation frequency of 100MHz. The algorithm employed is parallelizable for future prototypes, should a higher operation frequency be required

Unidad de linealización y normalización para un estimador de parámetros de uso en un sistema de optimización de energía en paneles fotovoltaicos

Proyecto de Graduación (Licenciatura en Ingeniería Electrónica) Instituto Tecnológico de Costa Rica, Escuela de Ingeniería Electrónica, 2016.Here, the design and veri_cation of an electrical current linealizing module written in Verilog, based on the IEEE 754 oating point standard, and using a CORDIC algorithm to perform a natural logarithm operation is presented. The system is to be used to optimize the e_ciency of photovoltaic panels with a non-linear I-V relation. The design is tested on a Digilint Nexys-4 FPGA board