Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

Design of an Ultra Low Power RFCMOS Transceiver for a Self-Powered IoT Node

In this thesis a transceiver characterized to consume ultra low power based in RFCMOS for a self-powered Internet of Things node is studied and designed. The transceiver consists in a simple Non-Coherent system, which means that the signal is picked up by the receiver based on energy detection, as a result it is one of the simplest existing transceivers once it does not need in the transmitter a complex pulse generator and certainly in the receiver as well. It is composed by an OOK modulator, a pulse generator that will determine the centre frequency and a driver amplifier connected to a 50W antenna for the transmitter. While in the receiver there is as first block a Low Noise Amplifier, a self-mixer that will prepare the signal for the integrator and a comparator working as a energy detector. The UWB transceiver will be able to operate with a centre frequency of 4.5 GHz and a bandwidth of at least 500 MHz. It is critical to notice that the system is consuming a value of 96 mW for the power and accomplishing the power spectrum density -43 dBm/MHz using an OOK modulation technique. The entire system was implemented with standard 130nm CMOS technology

RF Integrated Circuits for Energy Autonomous Sensor Nodes.

The exponential growth in the semiconductor industry has enabled computers to pervade our everyday lives, and as we move forward many of these computers will have form factors much smaller than a typical laptop or smartphone. Sensor nodes will soon be deployed ubiquitously, capable of capturing information of their surrounding environment. The next step is to connect all these different nodes together into an entire interconnected system. This “Internet of Things” (IoT) vision has incredible potential to change our lives commercially, societally, and personally. The backbone of IoT is the wireless sensor node, many of which will operate under very rigorous energy constraints with small batteries or no batteries at all. It has been shown that in sensor nodes, radio communication is one of the biggest bottlenecks to ultra-low power design. This research explores ways to reduce energy consumption in radios for wireless sensor networks, allowing them to run off harvested energy, while maintaining qualities that will allow them to function in a real world, multi-user environment. Three different prototypes have been designed demonstrating these techniques. The first is a sensitivity-reduced nanowatt wake-up radio which allows a sensor node to actively listen for packets even when the rest of the node is asleep. CDMA codes and interference rejection reduce the potential for energy-costly false wake-ups. The second prototype is a full transceiver for a body-worn EKG sensor node. This transceiver is designed to have low instantaneous power and is able to receive 802.15.6 Wireless Body Area Network compliant packets. It uses asymmetric communication including a wake-up receiver based on the previous design, UWB transmitter and a communication receiver. The communication receiver has 10 physical channels to avoid interference and demodulates coherent packets which is uncommon for low power radios, but dictated by the 802.15.6 standard. The third prototype is a long range transceiver capable of >1km communication range in the 433MHz band and able to interface with an existing commercial radio. A digitally assisted baseband demodulator was designed which enables the ability to perform bit-level as well as packet-level duty cycling which increases the radio's energy efficiency.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/110432/1/nerobert_1.pd

Techniques for Frequency Synthesizer-Based Transmitters.

Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd

Design of a Class-D RF power amplifier in CMOS technology

In this thesis an RF Class-D Power Amplifier is presented. The analysis of the Class-D amplifier considering ideal components has shown that the drain efficiency of 100% can be achieved. The output power and the drain efficiency are degraded by the internal resistance of each component. A driver is used to drive the gate capacitances of the Class-D amplifier. Both driver and amplifier are implemented with CMOS inverters. The size of the inverters in the driver is scaled down by a factor of 3 relatively to the preceding stage. The first being the inverter of the Class-D amplifier. At the output a 3rd order Butterworth bandpass filter is implemented. A non-ideal analysis of the Class-D amplifier is performed to create a base model which is used to aid in the design of the circuit. The RF Class-D Power Amplifier with the operation frequency of 2.4GHz was implemented with standard 130 nm CMOS technology. Two simulations were taken into account considering ideal and pre-layout components in the output filter. The following results were obtained when using ideal components: the output power of 6.91 dBm, the drain efficiency of 40% and the overall efficiency of 23%. Using pre-layout components the results were the following: the output power of 0.317 dBm the drain and overall efficiency of 8.6% and 4.9%, respectively

Receiver Front-Ends in CMOS with Ultra-Low Power Consumption

Historically, research on radio communication has focused on improving range and data rate. In the last decade, however, there has been an increasing demand for low power and low cost radios that can provide connectivity with small devices around us. They should be able to offer basic connectivity with a power consumption low enough to function extended periods of time on a single battery charge, or even energy scavenged from the surroundings. This work is focused on the design of ultra-low power receiver front-ends intended for a receiver operating in the 2.4GHz ISM band, having an active power consumption of 1mW and chip area of 1mm². Low power consumption and small size make it hard to achieve good sensitivity and tolerance to interference. This thesis starts with an introduction to the overall receiver specifications, low power radio and radio standards, front-end and LO generation architectures and building blocks, followed by the four included papers. Paper I demonstrates an inductorless front-end operating at 915MHz, including a frequency divider for quadrature LO generation. An LO generator operating at 2.4GHz is shown in Paper II, enabling a front-end operating above 2GHz. Papers III and IV contain circuits with combined front-end and LO generator operating at or above the full 2.45GHz target frequency. They use VCO and frequency divider topologies that offer efficient operation and low quadrature error. An efficient passive-mixer design with improved suppression of interference, enables an LNA-less design in Paper IV capable of operating without a SAW-filter

Design of Low-Power Transmitter and Receiver Front End

This thesis focuses on the design of "RF front-end blocks" for the transmitter and receiver. The blocks include the low noise amplifier (LNA) and mixer downconversion at the receiving side, while the power amplifier includes the pre-driver circuit, and mixer up-conversion at the transmitter side. All of the blocks were designed in a 65nm design kit. The basics of these RF blocks are first described in chapters two to four. After that, the general principle of operations is then described and different topologies are discussed. In chapter 5 the proposed design is discussed. The proposed design is composed of a differential IDCS narrow band LNA, with a passive down-conversion mixer on the receiving side, designed for bluetooth low energy (BLE) applications, that operates at 2.4 GHz with a 1.2 V supply voltage. The overall conversion gain at the receiving side was found to be greater than 13 dB with a double side band noise figure of 8.3 dB having a 1 dB compression point of -11.8 dB, and with IIP3 of -2.06 dBm having a power consumption of 251 μwatts. On the transmission side, a power amplifier with a pre-driver circuit and a passive up-conversion mixer has been designed to operate at a 1.2 V supply at the frequency of operation 2.4 GHz, having overall gain of 24 dB with maximum power added efficiency of 34% when using maximum output power of 11 dBm. The Cadence virtuoso design kit was used for simulation. Additionally, the layout considerations were discussed, followed by presentation of the post-layout results and graphs, and, finally, some conclusions have been drawn

Analysis and Design of a Transmitter for Wireless Communications in CMOS Technology

The number of wireless devices has grown tremendously over the last decade. Great technology improvements and novel transceiver architectures and circuits have enabled an astonishingly expanding set of radio-frequency applications. CMOS technology played a key role in enabling a large-scale diffusion of wireless devices due to its unique advantages in cost and integration. Novel digital-intensive transceivers have taken full advantage of CMOS technology scaling predicted by Moore's law. Die-shrinking has enabled ubiquitous diffusion of low-cost, small form factor and low power wireless devices. However, Radio Frequency (RF) Power Amplifiers (PA) transceiver functionality is historically implemented in a module which is separated from the CMOS core of the transceiver. The PA is traditionally dictating power and battery life of the transceiver, thus justifying its implementation in a tailored technology. By contrast, a fully integrated CMOS transceiver with no external PA would hugely benefit in terms of reduced area and system complexity. In this work, a fully integrated prototype of a Switched-Capacitor Power Amplifier (SCPA) has been implemented in a 28nm CMOS technology. The SCPA provides the functionalities of a PA and of a Radio-Frequency Digital-to-Analog Converter (RF-DAC) in a monolithic CMOS device. The switching output stage of the SCPA enables this circuital topology to reach high efficiencies and offers excellent power handling capabilities. In this work, the properties of the SCPA are analyzed in an extensive and detailed dissertation. Nowadays Wireless Communications operate in a very crowded spectrum, with strict coexistence requirements, thus demanding a strong linearity to the RF-DAC section of the SCPA. A great part of the work of designing a good SCPA is in fact designing a good RF-DAC. To enhance RF-DAC linearity, a precision of the timing of the elements up to the ps range is required. The use of a single core-supply voltage in the whole circuit including the CMOS inverter of the switching output stage enables the use of minimum size devices, improving accuracy and speed in the timing of the elements. The whole circuit operates therefore on low core-supply voltage. Throughout this work, a detailed analysis carefully describes the electromagnetic structures which maximize power and efficiency of low-voltage SCPAs. Due to layout issues subsequent to limited available voltages, however, there is a practical limitation in the maximum achievable power of low-voltage SCPAs. In this work, a Multi-Port Monolithic Power Combiner (PC) is introduced to overcome this limitation and further enhance total achieved system power. The PC sums the power of a collection of SCPAs to a single output, allowing higher output powers at a high efficiency. Benefits, drawbacks and design of SCPA PCs are discussed in this work. The implemented circuit features the combination of four differential SCPAs through a four-way monolithic PC and is simulated to obtain a maximum drain efficiency of 44% at a peak output power of 29dBm on 1.1V supply voltage. Extensive spectrum analysis offers full evaluation of system performances. After exploring state-of-the-art possibilities offered by an advanced 28nm CMOS technology, this work predicts through rigorous theoretical analysis the expected evolution of SCPA performances with the scaling of CMOS Technologies. The encouraging forecast further emphasizes the importance of SCPA circuits for the future of high-performance Wireless Communications

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