Low power LVDS transceiver for AER links with burst mode operation capability

This paper presents the design and simulation of an LVDS transceiver intended to be used in serial AER links. Traditional implementations of LVDS serial interfaces require a continuous data flow between the transmitter and the receiver to keep the synchronization. However, the serial AER-LVDS interface proposed in [2] operates in a burst mode, having long times of silence without data transmission. This can be used to reduce the power consumption by switching off the LVDS circuitry during the pauses. Moreover, a fast recovery time after pauses must be achieved to not slow down the interface operation. The transceiver was designed in a 90 nm technology. Extensive simulations have been performed demonstrating a 1 Gbps data rate operation for all corners in post-layout simulations. Driver and receiver take up an area of 100x215 m2 and 100x140 m2 respectively.Unión Europea 216777 (NABAB)Ministerio de Ciencia y Tecnología TEC2006-11730-C03-01 (SAMANTA II)Junta de Andalucía P06-TIC-0141

Design and Performance of the Data Acquisition System for the NA61/SHINE Experiment at CERN

This paper describes the hardware, firmware and software systems used in data acquisition for the NA61/SHINE experiment at the CERN SPS accelerator. Special emphasis is given to the design parameters of the readout electronics for the 40m^3 volume Time Projection Chamber detectors, as these give the largest contribution to event data among all the subdetectors: events consisting of 8bit ADC values from 256 timeslices of 200k electronic channels are to be read out with ~100Hz rate. The data acquisition system is organized in "push-data mode", i.e. local systems transmit data asynchronously. Techniques of solving subevent synchronization are also discussed.Comment: 14 pages, 13 figure

Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 um CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from prototype circuits and from irradiation studies with 24 GeV protons up to 57 Mrad (1.9 x 10e15 p/cm2).Comment: 8th Tropical Seminar on Innovative Particle and Radiation Detectors, Siena, Italy (2002

The SST Fully-Synchronous Multi-GHz Analog Waveform Recorder with Nyquist-Rate Bandwidth and Flexible Trigger Capabilities

The design and performance of a fully-synchronous multi-GHz analog transient waveform recorder I.C. ("SST") with fast and flexible trigger capabilities is presented. The SST's objective is to provide multi-GHz sample rates with intrinsically-stable timing, Nyquist-rate sampling and high trigger bandwidth, wide dynamic range and simple operation. Containing 4 channels of 256 samples per channel, the SST is fabricated in an inexpensive 0.25 micrometer CMOS process and uses a high-performance package that is 8 mm on a side. It has a 1.9V input range on a 2.5V supply, exceeds 12 bits of dynamic range, and uses ~128 mW while operating at 2 G-samples/s and full trigger rates. With a standard 50 Ohm input source, the SST exceeds ~1.5 GHz -3 dB bandwidth. The SST's internal sample clocks are generated synchronously via a shift register driven by an external LVDS oscillator running at half the sample rate (e.g., a 1 GHz oscillator yields 2 G-samples/s). Because of its purely-digital synchronous nature, the SST has ps-level timing uniformity that is independent of sample frequencies spanning over 6 orders of magnitude: from under 2 kHz to over 2 GHz. Only three active control lines are necessary for operation: Reset, Start/Stop and Read-Clock. When operating as common-stop device, the time of the stop, modulo 256 relative to the start, is read out along with the sampled signal values. Each of the four channels integrates dual-threshold trigger circuitry with windowed coincidence features. Channels can discriminate signals with ~1mV RMS resolution at >600 MHz bandwidth.Comment: 3 pages, 6 figures, 1 table, submitted for publication in the Conference Record of the 2014 IEEE Nuclear Science Symposium, Seattle, WA, November 201

CMOS VLSI correlator design for radio-astronomical signal processing : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand

Multi-element radio telescopes employ methods of indirect imaging to capture the image of the sky. These methods are in contrast to direct imaging methods whereby the image is constructed from sensor measurements directly and involve extensive signal processing on antenna signals. The Square Kilometre Array, or the SKA, is a future radio telescope of this type that, once built, will become the largest telescope in the world. The unprecedented scale of the SKA requires novel solutions to be developed for its signal processing pipeline one of the most resource-consuming parts of which is the correlator. The SKA uses the FX correlator construction that consists of two parts: the F part that translates antenna signals into frequency domain and the X part that cross-correlates these signals between each other. This research focuses on the integrated circuit design and VLSI implementation issues of the X part of a very large FX correlator in 28 nm and 130 nm CMOS. The correlator’s main processing operation is the complex multiply-accumulation (CMAC) for which custom 28 nm CMAC designs are presented and evaluated. Performance of various memories inside the correlator also affects overall efficiency, and input-buffered and output-buffered approaches are considered with the goal of improving upon it. For output-buffered designs, custom memory control circuits have been designed and prototyped in 130 nm that improve upon eDRAM by taking advantage of sequential access patterns. For the input-buffered architecture, a new scheme is proposed that decreases the usage of the input-buffer memory by a third by making use of multiple accumulators in every CMAC. Because cross-correlation is a very data-intensive process, high-performance SerDes I/O is essential to any practical ASIC implementation. On the I/O design, the 28 nm full-rate transmitter delivering 15 Gbps per lane is presented. This design consists of the scrambler, the serialiser, the digital VCO with analog fine-tuning and the SST driver including features of a 4-tap FFE, impedance tuning and amplitude tuning

Optical Link of the Atlas Pixel Detector

The on-detector optical link of the ATLAS pixel detector contains radiation-hard receiver chips to decode bi-phase marked signals received on PIN arrays and data transmitter chips to drive VCSEL arrays. The components are mounted on hybrid boards (opto-boards). We present results from the irradiation studies with 24 GeV protons up to 32 Mrad (1.2 x 10^15 p/cm^2) and the experience from the production.Comment: 9th ICATPP Conference, Como, Ital

A high speed Tri-Vision system for automotive applications

Purpose: Cameras are excellent ways of non-invasively monitoring the interior and exterior of vehicles. In particular, high speed stereovision and multivision systems are important for transport applications such as driver eye tracking or collision avoidance. This paper addresses the synchronisation problem which arises when multivision camera systems are used to capture the high speed motion common in such applications. Methods: An experimental, high-speed tri-vision camera system intended for real-time driver eye-blink and saccade measurement was designed, developed, implemented and tested using prototype, ultra-high dynamic range, automotive-grade image sensors specifically developed by E2V (formerly Atmel) Grenoble SA as part of the European FP6 project – sensation (advanced sensor development for attention stress, vigilance and sleep/wakefulness monitoring). Results : The developed system can sustain frame rates of 59.8 Hz at the full stereovision resolution of 1280 × 480 but this can reach 750 Hz when a 10 k pixel Region of Interest (ROI) is used, with a maximum global shutter speed of 1/48000 s and a shutter efficiency of 99.7%. The data can be reliably transmitted uncompressed over standard copper Camera-Link® cables over 5 metres. The synchronisation error between the left and right stereo images is less than 100 ps and this has been verified both electrically and optically. Synchronisation is automatically established at boot-up and maintained during resolution changes. A third camera in the set can be configured independently. The dynamic range of the 10bit sensors exceeds 123 dB with a spectral sensitivity extending well into the infra-red range. Conclusion: The system was subjected to a comprehensive testing protocol, which confirms that the salient requirements for the driver monitoring application are adequately met and in some respects, exceeded. The synchronisation technique presented may also benefit several other automotive stereovision applications including near and far-field obstacle detection and collision avoidance, road condition monitoring and others.Partially funded by the EU FP6 through the IST-507231 SENSATION project.peer-reviewe