A 13-bit, 2.2-MS/s, 55-mW multibit cascade ΣΔ modulator in CMOS 0.7-μm single-poly technology

This paper presents a CMOS 0.7-μm ΣΔ modulator IC that achieves 13-bit dynamic range at 2.2 MS/s with an oversampling ratio of 16. It uses fully differential switched-capacitor circuits with a clock frequency of 35.2 MHz, and has a power consumption of 55 mW. Such a low oversampling ratio has been achieved through the combined usage of fourth-order filtering and multibit quantization. To guarantee stable operation for any input signal and/or initial condition, the fourth-order shaping function has been realized using a cascade architecture with three stages; the first stage is a second-order modulator, while the others are first-order modulators - referred to as a 2-1-1mb architecture. The quantizer of the last stage is 3 bits, while the other quantizers are single bit. The modulator architecture and coefficients have been optimized for reduced sensitivity to the errors in the 3-bit quantization process. Specifically, the 3-bit digital-to-analog converter tolerates 2.8% FS nonlinearity without significant degradation of the modulator performance. This makes the use of digital calibration unnecessary, which is a key point for reduced power consumption. We show that, for a given oversampling ratio and in the presence of 0.5% mismatch, the proposed modulator obtains a larger signal-to-noise-plus-distortion ratio than previous multibit cascade architectures. On the other hand, as compared to a 2-1-1single-bit modulator previously designed for a mixed-signal asymmetrical digital subscriber line modem in the same technology, the modulator in this paper obtains one more bit resolution, enhances the operating frequency by a factor of two, and reduces the power consumption by a factor of four.Comisión Interministerial de Ciencia y Tecnología TIC97-0580European Commission ESPRIT 879

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

A SigmaDelta modulator for digital hearing instruments using 0.18 mum CMOS technology.

This thesis develops the design methodology for a low-voltage low-power SigmaDelta Modulator, realized using a switched op-amp technique that can be used in a hearing instrument. Switched op-amp implementation allows scaling down the design to the latest CMOS technology. A single-loop second-order SigmaDelta Modulator topology is chosen. The modulator circuit features reduced complexity, area reduction and low conversion energy. The modulator has a sampling rate of 8.2 MHz with an over-sampling ratio (OSR) of 256 to provide an audio bandwidth of 16 kHz. The modulator is implemented in a 0.18 mum digital CMOS technology with metal-to-metal sandwich structure capacitors. The modulator operates with a supply voltage of 1.8 V. The active area is 0.403 mm2. The modulator achieves a 98 dB signal-to-noise-and-distortion ratio (SNDR) and a 100 dB dynamic range (DR) at a Nyquist conversion rate of 32 kHz and consumes 1321 muW with a joule/conversion figure of merit equal to 161 x 10-12 J/s. The design methodology is developed through the extensive use of simulation tools. The behaviour simulation is carried out using Matlab/SIMULINK while circuits are simulated with Hspice using the Cadence design tools. Full-custom layout for the analog and the digital circuits is performed using the Cadence design tool. Post-processing simulation of the extracted modulator with parasitic verifies that results meet the requirements. The design has been sent to CMC for fabrication. Source: Masters Abstracts International, Volume: 43-03, page: 0947. Adviser: W. C. Miller. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Design and Assembly of High-Temperature Signal Conditioning System on LTCC with Silicon Carbide CMOS Circuits

The objective of the work described in this dissertation paper is to develop a prototype electronic module on a low-temperature co-fired ceramic (LTCC) material. The electronic module would perform signal conditioning of sensor signals (thermocouples) operating under extreme conditions for applications like gas turbines to collect data on the health of the turbine blades during operation so that the turbines do not require shutdown for inspection to determine if maintenance is required. The collected data can indicate when such shutdowns, which cost $1M per day, should be scheduled and maintenance actually performed. The circuits for the signal conditioning system within the prototype module must survive the extreme temperature, pressure, and centrifugal force, or G-force, present in these settings. Multiple fabrication runs on different integrated silicon carbide (SiC) process technologies have been carried out to meet the system requirements. The key circuits described in this dissertation are - two-stage op amp topologies and voltage reference, which are designed and fabricated in a new SiC CMOS process. The SiC two-stage op amp with PFET differential input pair showed 48.9 dB of DC gain at 500oC. The voltage reference is the first in SiC CMOS technology to employ an op amp-based topology. The op amp circuit in the voltage reference is a two-stage with NFET differential input pair that uses the indirect compensation technique for the first time in the SiC CMOS process to provide 42.5 dB gain at 350oC. The designed prototype module implemented with these circuits was verified to provide signal conditioning and signal transmission at 300oC. The signal transmission circuit on the module was also verified to operate with a resonant inductive wireless power transfer method at a frequency of 11.8 MHz for the first time. A second prototype module was also developed with the previously fabricated 1.2 µm SiC CMOS process. The second module was successfully tested (with wired power supply) to operate at 440oC inside a probe-station and also verified for the first time to sustain signal transmission (34.65 MHz) capability inside a spin-rig at a rotational speed of 10,920 rpm. All designed modules have dimensions of (length) 68.5 mm by (width) 34.3 mm to conform to the physical size requirements of the gas turbine blade

Implicit feed-forward compensated op-amp with split pairs

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.Board of Regents, University of Texas Syste

On the optimum design of regulated cascode operational transconductance amplifiers

An optimal design procedure to achieve minimum power consump-tion for a given technology and gain bandwidth is presented. Reg-ulated cascode gain enhancement is used to ensure sufficient DC-gain at minimum gate length transistors. To validate the approach five folded cascode OTA’s have been implemented, spanning a bias range of 1A- 10mA, with measured unity-gain bandwidths within 20 % of the designed value. For 17 mW at 3 V, a 0.5 m CMOS OTA achieves 630 MHz with 51 phase margin. The method has been applied in the design of a 3rd order modulator for GSM receivers. The modulator consumes 2.8 mW at 3 V and has a dy-namic range of 86 dB for a 100 kHz input signal bandwidth.

Multi-stage noise shaping (MASH) delta-sigma modulators for wideband and multi-standard applications

Imperial Users onl