75,745 research outputs found

    Photonic integrated Mach-Zehnder interferometer with an on-chip reference arm for optical coherence tomography

    Get PDF
    Optical coherence tomography (OCT) is a noninvasive, three-dimensional imaging modality with several medical and industrial applications. Integrated photonics has the potential to enable mass production of OCT devices to significantly reduce size and cost, which can increase its use in established fields as well as enable new applications. Using silicon nitride (Si(3)N(4)) and silicon dioxide (SiO(2)) waveguides, we fabricated an integrated interferometer for spectrometer-based OCT. The integrated photonic circuit consists of four splitters and a 190 mm long reference arm with a foot-print of only 10 × 33 mm(2). It is used as the core of a spectral domain OCT system consisting of a superluminescent diode centered at 1320 nm with 100 nm bandwidth, a spectrometer with 1024 channels, and an x-y scanner. The sensitivity of the system was measured at 0.25 mm depth to be 65 dB with 0.1 mW on the sample. Using the system, we imaged human skin in vivo. With further optimization in design and fabrication technology, Si(3)N(4)/SiO(2) waveguides have a potential to serve as a platform for passive photonic integrated circuits for OCT

    Thermosonic flip chip interconnection using electroplated copper column arrays

    No full text
    Published versio

    The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    Full text link
    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns within a total of 256 bins. The chip also comprises a pipeline to store data from 128 events which is required for a deadtime-free trigger and data acquisition system. We report on the development, installation, and commissioning of the front-end electronics, including the grounding and noise suppression schemes, and discuss its performance in the HERA-B experiment

    A novel camera type for very high energy gamma-ray astronomy based on Geiger-mode avalanche photodiodes

    Full text link
    Geiger-mode avalanche photodiodes (G-APD) are promising new sensors for light detection in atmospheric Cherenkov telescopes. In this paper, the design and commissioning of a 36-pixel G-APD prototype camera is presented. The data acquisition is based on the Domino Ring Sampling (DRS2) chip. A sub-nanosecond time resolution has been achieved. Cosmic-ray induced air showers have been recorded using an imaging mirror setup, in a self-triggered mode. This is the first time that such measurements have been carried out with a complete G-APD camera.Comment: 9 pages with 11 figure

    A double-sided silicon micro-strip super-module for the ATLAS inner detector upgrade in the high-luminosity LHC

    Get PDF
    The ATLAS experiment is a general purpose detector aiming to fully exploit the discovery potential of the Large Hadron Collider (LHC) at CERN. It is foreseen that after several years of successful data-taking, the LHC physics programme will be extended in the so-called High-Luminosity LHC, where the instantaneous luminosity will be increased up to 5 × 1034 cm−2 s−1. For ATLAS, an upgrade scenario will imply the complete replacement of its internal tracker, as the existing detector will not provide the required performance due to the cumulated radiation damage and the increase in the detector occupancy. The current baseline layout for the new ATLAS tracker is an all-silicon-based detector, with pixel sensors in the inner layers and silicon micro-strip detectors at intermediate and outer radii. The super-module is an integration concept proposed for the strip region of the future ATLAS tracker, where double-sided stereo silicon micro-strip modules are assembled into a low-mass local support structure. An electrical super-module prototype for eight double-sided strip modules has been constructed. The aim is to exercise the multi-module readout chain and to investigate the noise performance of such a system. In this paper, the main components of the current super-module prototype are described and its electrical performance is presented in detail

    Two-Level Rectilinear Steiner Trees

    Get PDF
    Given a set PP of terminals in the plane and a partition of PP into kk subsets P1,...,PkP_1, ..., P_k, a two-level rectilinear Steiner tree consists of a rectilinear Steiner tree TiT_i connecting the terminals in each set PiP_i (i=1,...,ki=1,...,k) and a top-level tree TtopT_{top} connecting the trees T1,...,TkT_1, ..., T_k. The goal is to minimize the total length of all trees. This problem arises naturally in the design of low-power physical implementations of parity functions on a computer chip. For bounded kk we present a polynomial time approximation scheme (PTAS) that is based on Arora's PTAS for rectilinear Steiner trees after lifting each partition into an extra dimension. For the general case we propose an algorithm that predetermines a connection point for each TiT_i and TtopT_{top} (i=1,...,ki=1,...,k). Then, we apply any approximation algorithm for minimum rectilinear Steiner trees in the plane to compute each TiT_i and TtopT_{top} independently. This gives us a 2.372.37-factor approximation with a running time of O(PlogP)\mathcal{O}(|P|\log|P|) suitable for fast practical computations. The approximation factor reduces to 1.631.63 by applying Arora's approximation scheme in the plane

    Monolithic Pixel Sensors in Deep-Submicron SOI Technology

    Full text link
    Monolithic pixel sensors for charged particle detection and imaging applications have been designed and fabricated using commercially available, deep-submicron Silicon-On-Insulator (SOI) processes, which insulate a thin layer of integrated full CMOS electronics from a high-resistivity substrate by means of a buried oxide. The substrate is contacted from the electronics layer through vias etched in the buried oxide, allowing pixel implanting and reverse biasing. This paper summarizes the performances achieved with a first prototype manufactured in the OKI 0.15 micrometer FD-SOI process, featuring analog and digital pixels on a 10 micrometer pitch. The design and preliminary results on the analog section of a second prototype manufactured in the OKI 0.20 micrometer FD-SOI process are briefly discussed.Comment: Proceedings of the PIXEL 2008 International Workshop, FNAL, Batavia, IL, 23-26 September 2008. Submitted to JINST - Journal of Instrumentatio

    The MINERν\nuA Data Acquisition System and Infrastructure

    Full text link
    MINERν\nuA (Main INjector ExpeRiment ν\nu-A) is a new few-GeV neutrino cross section experiment that began taking data in the FNAL NuMI (Fermi National Accelerator Laboratory Neutrinos at the Main Injector) beam-line in March of 2010. MINERν\nuA employs a fine-grained scintillator detector capable of complete kinematic characterization of neutrino interactions. This paper describes the MINERν\nuA data acquisition system (DAQ) including the read-out electronics, software, and computing architecture.Comment: 34 pages, 16 figure
    corecore