Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

Design and Optimization of Superjunction Vertical DMOS Power Transistors using Sentaurus Device Simulation

Vertical double-diffused metal oxide semiconductor (VDMOS) power transistor has been studied. The use of superjunction (SJ) in the drift region of VDMOS has been evaluated using three-dimensional device simulation. All relevant physical models in Sentaurus are turned on. The VDMOS device doping profile is obtained from process simulation. The superjunction VDMOS performance in off-state breakdown voltage and specific on-resistance is compared with that in conventional VDMOS structure. In addition, electrical parameters such as threshold voltage and charge balance are also examined. Increasing the superjunction doping in the drift region of VDMOS reduces the on-resistance by 26%, while maintaining the same breakdown voltage and threshold voltage compared to that of the conventional VDMOS power transistor with similar device design without using a superjunction

Development, fabrication, and characterization of a vertical-diffused MOS process for power RF applications

High power radio frequency (RF) applications have become important because of a growing demand from the wireless market. With their superior switching speed, power Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) have become one of the well-known technologies used in high power RF systems. The primary focus of this thesis work was the development, fabrication, and characterization of discrete Verticaldrain lateral-Diffused MOS (VDMOS) power transistors using an interdigitated source/gate design. Several types of high power devices were also presented for comparison to the VDMOS structure. This thesis describes the overall purpose and the objectives of the proposed project, and provides the methodology used to complete these objectives. This project supports a new development initiative of the project sponsor, Spectrum Devices, Inc., who has been working with RIT in power bipolar technologies over the last two years. The process steps to create a 50 V power VDMOS transistor structure were designed using Silvaco ATHENA (SUPREM-IV) process simulation. Typical power VDMOS transistor fabrication steps were used as a starting point with modifications to include Faraday and UIS implant steps to address certain parasitic effects. The Faraday shield implant was performed to shift the parasitic gate- field capacitance over to the input side of the device, which should dramatically improve the frequency response of the device. The UIS implant was used to reduce the parasitic BJT of a power VDMOS transistor. The implementation of the proposed structure also eliminated the need for an added masking operation for each implant step, and kept the structure self- aligned to the gate stack. This eliminated potential overlay tolerances and error that may be encountered in photolithography steps. The initial process parameters were carefully varied and adjusted to meet the target specifications (such as threshold voltage, breakdown voltage, gate oxide thickness, etc.) using ATHENA and ATLAS simulation software. After the device fabrication was completed, DC testing was performed on the fabricated VDMOS transistors both at RIT and at Spectrum Devices. A successful extraction of the transfer curves, family of curves, and breakdown voltage plots both in low and high current settings was achieved. The designed process produced a power VDMOS with a breakdown voltage of up to 180 V, a threshold voltage of ~3.8 V, a transconductance up to ~7 mhos, and an operating current of nearly 5 A. The experimental results were compared to the target specification provided by Spectrum Devices. In addition, impacts of the Faraday shield implant on the breakdown voltage and terminal capacitances of a VDMOS device were verified through DC testing. Preliminary wafer- level AC testing was performed and demonstrated the functional performance of the device up to 100 kHz frequency range. Although it would be interesting to see the impact of UIS implant step on a device performance, no AC test was yet to be performed. This work presented the first power VDMOS transistors successfully fabricated and characterized at RIT. With the data and information obtained from this thesis project, process modifications and adjustments should yield devices with improved performance

Improved electrothermal ruggedness in SiC MOSFETs compared with silicon IGBTs

A 1.2-kV/24-A SiC-MOSFET and a 1.2-kV/30-A Si-Insulated gate bipolar transistor (IGBT) have been electrothermally stressed in unclamped inductive switching conditions at different ambient temperatures ranging from -25 °C to 125 °C. The devices have been stressed with avalanche currents at their rated currents and 40% higher. The activation of the parasitic bipolar junction transistor (BJT) during avalanche mode conduction results from the increased body resistance causing a voltage drop between the source and body, greater than the emitter-base voltage of the parasitic BJT. Because the BJT current and temperature relate through a positive feedback mechanism, thermal runaway results in the destruction of the device. It is shown that the avalanche power sustained before the destruction of the device increases as the ambient temperature decreases. SiC MOSFETs are shown to be able to withstand avalanche currents equal to the rated forward current at 25 °C, whereas IGBTs cannot sustain the same electrothermal stress. SiC MOSFETs are also shown to be capable of withstanding avalanche currents 40% above the rated forward current though only at reduced temperatures. An electrothermal model has been developed to explain the temperature dependency of the BJT latchup, and the results are supported by finite-element models

Prikaz stanja silicijevih MOS upravljanih učinskih sklopova i PiN ispravljača

Revolutionary advances and developments have been made in power semiconductor device technologies during the last decades which have allowed the improvement of power electronic systems in terms of their efficiency and reliability. The advent of MOS-gated power switches such as the power MOSFET and the IGBT showing high input impedance has been a real breakthrough in the design and fabrication of power electronic systems. This paper reviews the recent progress in the development of Si MOS-gated power devices and rectifiers. The evolution of these devices’ technologies together with the introduction of revolutionary device concepts is also discussed. Concretely, the introduction of trench technologies for power MOSFETs and the use of the super-junction concept for breaking the 1D-silicon limit are highlighted. Developments in IGBTs such as those based on the use of thin wafers and strategies for optimising the plasma distribution in PT IGBTs during the on-state are also addressed. Finally, advances in PiN diode technologies including new concepts for both the anode and the cathode structures are also reviewed. These approaches have allowed the reduction of the PiN total losses and a soft reverse recovery behaviour, leading to a more rugged device.U posljednjim desetljećima svjedočimo razvoju sustava učinske elektronike u pogledu povećanja efikasnosti i pouzdanosti. Napredak je omogućen zahvaljujući izvanrednom napredku koji je postignut na području učinskih poluvodiča. Pojava MOS upravljanih učinskih sklopova s visokom ulaznom impedancijom, kao što su MOSFET i IGBT, rezultirao je probojem u projektiranju i proizvodnji sustava učinske elekronike. Ovaj članak daje uvid u napredak koji je u posljednje vrijeme ostvaren u razvoju silicijeve MOS upravljane učinske elektronike i ispravljača. Uz dosadašnji razvoj tehnologije navedenih komponenata, u članku je uključen i osvrt na revolucionarne koncepte budućeg razvoja. Konkretno, u radu su objašnjene tehnologija rova za MOSFET i korištenje koncepta super spoja za probijanje granice jednodimenzionalnog silicija. Razmatrana su i poboljšanja IGBT-ova koja se baziraju na uporabi tankih pločica a strategijama optimiranja distribucije plazme u PT IGBT-ovima za vrijeme aktivnog stanja. Konačno, prikazan je i napredak u tehnologiji PiN dioda koji uključuje nove strukturalne koncepte katode i anode. Ovi pristupi su omogućili smanjenje ukupnih gubitaka PiN diode i blagu dinamiku reverznog oporavka, što rezultira povećanjem robusnosti sklopa

Novel 3-D IC technology

textFor many decades silicon based CMOS technology has made continual increase in drive current to achieve higher speed and lower power by scaling the gate length and the gate insulator thickness. The scaling becomes increasingly challenging because the devices are approaching physical quantum limits. Three-dimensional electronic devices, such as double gate, tri-gate and nanowire field-effect-transistors (FETs) provide an alternative solution because the ultra-thin fin or nanowire provides better electrostatic control of the device channel. Also high-[kappa] oxides lower the gate leakage current significantly, due to larger thickness for the same equivalent oxide thickness (EOT) compared with SiO₂ beyond the 22 nm node. Moreover, metal gate that avoids the poly-depletion effect in poly-Si gate has become mainstream semiconductor technology. The enabler technologies for high-[kappa] / metal gate 3D transistors include fabrication of high quality, vertical nanowire arrays, conformal metal and dielectric deposition and vertical patterning. One of the main focuses of this dissertation is developing a fabrication process flow to realize high performance MOSFETs with high-[kappa] oxide and metal gate on vertical silicon nanowire arrays. A variety of approaches to fabricating highly ordered silicon nanowire arrays have been achieved. Deep silicon etching process was developed and optimized for nanowire FETs. Process integration and patterning mythologies for high-[kappa] / metal gate were investigated and accomplished. 3-D electronic devices including nanowire capacitors, nanowire FETs and double gate MOSFETs for power applications were fabricated and characterized. The second part of this dissertation is about flexible electronics. Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for fabrication of inexpensive, high performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be pre-fabricated on bulk silicon wafer with conventional CMOS process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to produce thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).Electrical and Computer Engineerin

Power Metal-oxide-semiconductor Field-effect Transistor With Strained Silicon And Silicon Germanium Channel

With the development of modern electronics, the demand for high quality power supplies has become more urgent than ever. For power MOSFETs, maintaining the trend of reducing on-state resistance (conduction loss) without sacrificing switching performance is a severe challenge. In this work, our research is focused on implementing strained silicon and silicon germanium in power MOFETs to enhance carrier mobility, thus achieving the goal of reducing specific on-state resistance. We propose an N-channel super-lattice trench MOSFET, a P-channel sidewall channel trench MOSFET and P-Channel LDMOS with strained Si/SiGe channels. A set of fabrication processes highly compatible with conventional Si technology is developed to fabricate proposed devices. The mobility enhancement is observed to be 20%, 40% and 35% respectively for N-channel, Pchannel trench MOSFET and LDMOS respectively and the on-state resistance is reduced by 10%, 20% and 22% without sacrificing other device performance parameters

Study Of Ingaas Ldmos For Power Conversion Applications

In this work an n-channel In0.65Ga0.35As LDMOS with Al2O3 as gate dielectric is investigated. Instead of using traditional Si process for LDMOS, we suggest In0.65Ga0.35As as substitute material due to its higher electron mobility and its promising for power applications. The proposed 0.5-µm channel-length LDMOS cell is studied through device TCAD simulation tools. Due to different gate dielectric, comprehensive comparisons between In0.65Ga0.35As LDMOS and Si LDMOS are made in two ways, structure with the same cross-sectional dimension, and structure with different thickness of gate dielectric to achieve the same gate capacitance. The on-resistance of the new device shows a big improvement with no degradation on breakdown voltage over traditional device. Also it is indicated from these comparisons that the figure of merit(FOM) Ron·Qg of In0.65Ga0.35As LDMOS shows an average of 91.9% improvement to that of Si LDMOS. To further explore the benefit of using In0.65Ga0.35As LDMOS as switch in power applications, DC-DC buck converter is utilized to observe the performance of LDMOS in terms of power efficiency. The LDMOS performance is experimented with operation frequency of the circuit sweeping in the range from 100 KHz to 100 MHz. It turns out InGaAs LDMOS is good candidate for power applications

Conventional And Zvt Synchronous Buck Converter Design, Analysis, And Measurement

The role played by power converting circuits is extremely important to almost any electronic system built today. Circuits that use converters of any type depend on power that is consistent in form and reliable in order to properly function. In addition, today\u27s demands require more efficient use of energy, from large stationary systems such as power plants all the way down to small mobile devices such as laptops and cell phones. This places a need to reduce any losses to a minimum. The power conversion circuitry in a system is a very good place to reduce a large amount of unnecessary loss. This can be done using circuit topologies that are low loss in nature. For low loss and high performance, soft switching topologies have offered solutions in some cases. Also, limited study has been performed on device aging effects on switching mode power converting circuits. The impact of this effect on a converter\u27s overall efficiency is theoretically known but with little experimental evidence in support. In this thesis, non-isolated buck type switching converters will be the main focus. This type of power conversion is widely used in many systems for DC to DC voltage step down. Newer methods and topologies to raise converter power efficiency are discussed, including a new synchronous ZVT topology . Also, a study has been performed on device aging effects on converter efficiency. Various scenarios of voltage conversion, switching frequency, and circuit components as well as other conditions have been considered. Experimental testing has been performed in both cases, ZVT\u27s benefits and device aging effects, the results of which are discussed as well

Current Single Event Effects Compendium of Candidate Spacecraft Electronics for NASA

We present the results of single event effects (SEE) testing and analysis investigating the effects of radiation on electronics. This paper is a summary of test results