Binary operation procedure for thinning process and its VLSI implementation in a pixel array circuit

In this thesis, the design of a pixel array circuit for thinning process is presented. The research efforts of this work are on the two aspects: the processing algorithm and the circuit design. In the aspect of algorithm, a new thinning process is designed aiming at an easy implementation in a VLSI pixel array circuit. The computation is made in parallel and with a small number of direct data transfers among the neighboring pixels, which leads to a fast processing and fewer metal connections in the circuit. The effectiveness of the algorithm has been proved in the simulation. The other aspect of this work is the design of a pixel array circuit implementing the image acquisition and the proposed thinning proces

An Adaptable Foveating Vision Chip

Published versio

Digital implementation of the cellular sensor-computers

Two different kinds of cellular sensor-processor architectures are used nowadays in various applications. The first is the traditional sensor-processor architecture, where the sensor and the processor arrays are mapped into each other. The second is the foveal architecture, in which a small active fovea is navigating in a large sensor array. This second architecture is introduced and compared here. Both of these architectures can be implemented with analog and digital processor arrays. The efficiency of the different implementation types, depending on the used CMOS technology, is analyzed. It turned out, that the finer the technology is, the better to use digital implementation rather than analog

The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Scientific CCD technology at JPL

Charge-coupled devices (CCD's) were recognized for their potential as an imaging technology almost immediately following their conception in 1970. Twenty years later, they are firmly established as the technology of choice for visible imaging. While consumer applications of CCD's, especially the emerging home video camera market, dominated manufacturing activity, the scientific market for CCD imagers has become significant. Activity of the Jet Propulsion Laboratory and its industrial partners in the area of CCD imagers for space scientific instruments is described. Requirements for scientific imagers are significantly different from those needed for home video cameras, and are described. An imager for an instrument on the CRAF/Cassini mission is described in detail to highlight achieved levels of performance

Large-area CCD imagers for spacecraft applications

Backside illuminated CCD imagers with 100 x 160 resolution elements have been fabricated using double level metal technology. Detailed study of the optical performance of such arrays has been performed between 24 C and -40 C using data rates from 10 kHz to 1 MHz. A 400 x 400 array is presently being fabricated

Ge-based Medium Wave Infrared MCT 1280 × 1024 Focal Plane Detector

Medium-wave HgCdTe thin films grown on germanium-based substrates by molecular beam epitaxy were treated by large area n-on-p injection junction and flip-flop mixing process. The chips interconnected with low-noise and multimodal options readout circuit composed a 1280×1024 Medium-wave Infrared Focal Plane Cooling Detector whose pixel spacing was 15 microns. Its main photoelectric properties are average NETD equivalent to 18.5 mK, non-uniformity equivalent to 7.5%, operability equivalent to 98.97%. The paper also studies the substrate-removal technique on Germanium-based chip, which improves the stability and reliability of detector

Delta-doped hybrid advanced detector for low energy particle detection

A delta-doped hybrid advanced detector (HAD) is provided which combines at least four types of technologies to create a detector for energetic particles ranging in energy from hundreds of electron volts (eV) to beyond several million eV. The detector is sensitive to photons from visible light to X-rays. The detector is highly energy-sensitive from approximately 10 keV down to hundreds of eV. The detector operates with milliwatt power dissipation, and allows non-sequential readout of the array, enabling various advanced readout schemes

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1