52,499 research outputs found

    A Fault Tolerant 3-Phase Adjustable Speed Drive Topology with Common Mode Voltage Suppression

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    A fault tolerant adjustable speed drive (ASD) topology is introduced in this work. A conventional ASD topology is modified to address: a) drive vulnerability to semiconductor device faults b) input voltage sags c) motor vulnerability to effects of long leads and d) achieve active minimization of common mode (CM) voltage applied to the motor terminals. These objectives are attained by inclusion of an auxiliary IGBT inverter leg, three auxiliary diodes, and isolation - reconfiguration circuit. The design and operation of the proposed topology modifications are described for different modes; (A) Fault mode, (B) Auxiliary Sag Compensation (ASC) mode and (C) Active Common Mode Suppression mode. In case of fault and sag, the isolation and hardware reconfiguration are performed in a controlled manner using triacs/anti-parallel thyristors/solid state relays. In normal operation, the auxiliary leg is controlled to actively suppress common mode voltage. For inverter IGBT failures (short circuit and open circuit), the auxiliary leg is used as a redundant leg. During voltage sags, the auxiliary leg along with auxiliary diodes is operated as a boost converter. A current shaping control strategy is proposed for the ASC mode. A detailed analysis of common mode performance of the proposed topology is provided and a new figure of merit, Common Mode Distortion Ratio (CMDR) is introduced to compare the attenuation of common mode voltage with that of a conventional ASD topology for three different modulation strategies. The output filter design procedure is outlined. A design example is presented for an 80 kW ASD system and simulation results validate the proposed auxiliary leg based fault tolerant scheme. Experimental results from a scaled prototype rated at 1 hp prototype also confirm the operation. The common mode analysis is also validated with the experimental results

    Insights into dynamic tuning of magnetic-resonant wireless power transfer receivers based on switch-mode gyrators

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    Magnetic-resonant wireless power transfer (WPT) has become a reliable contactless source of power for a wide range of applications. WPT spans different power levels ranging from low-power implantable devices up to high-power electric vehicles (EV) battery charging. The transmission range and efficiency of WPT have been reasonably enhanced by resonating the transmitter and receiver coils at a common frequency. Nevertheless, matching between resonance in the transmitter and receiver is quite cumbersome, particularly in single-transmitter multi-receiver systems. The resonance frequency in transmitter and receiver tank circuits has to be perfectly matched, otherwise power transfer capability is greatly degraded. This paper discusses the mistuning effect of parallel-compensated receivers, and thereof a novel dynamic frequency tuning method and related circuit topology and control is proposed and characterized in the system application. The proposed method is based on the concept of switch-mode gyrator emulating variable lossless inductors oriented to enable self-tunability in WPT receiversPeer ReviewedPostprint (published version

    An Offset Cancelation Technique for Latch Type Sense Amplifiers

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    An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

    Fuzzy second order sliding mode control of a unified power flow controller

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    Purpose. This paper presents an advanced control scheme based on fuzzy logic and second order sliding mode of a unified power flow controller. This controller offers advantages in terms of static and dynamic operation of the power system such as the control law is synthesized using three types of controllers: proportional integral, and sliding mode controller and Fuzzy logic second order sliding mode controller. Their respective performances are compared in terms of reference tracking, sensitivity to perturbations and robustness. We have to study the problem of controlling power in electric system by UPFC. The simulation results show the effectiveness of the proposed method especiallyin chattering-free behavior, response to sudden load variations and robustness. All the simulations for the above work have been carried out using MATLAB / Simulink. Various simulations have given very satisfactory results and we have successfully improved the real and reactive power flows on a transmission lineas well as to regulate voltage at the bus where it is connected, the studies and illustrate the effectiveness and capability of UPFC in improving power.В настоящей статье представлена усовершенствованная схема управления, основанная на нечеткой логике и режиме скольжения второго порядка унифицированного контроллера потока мощности. Данный контроллер обладает преимуществами с точки зрения статической и динамической работы энергосистемы, например, закон управления синтезируется с использованием трех типов контроллеров: пропорционально-интегрального, контроллера скользящего режима и контроллера скользящего режима нечеткой логики второго порядка. Их соответствующие характеристики сравниваются с точки зрения отслеживания эталонов, чувствительности к возмущениям и надежности. Необходимо изучить проблему управления мощностью в энергосистеме с помощью унифицированного контроллера потока мощности (UPFC). Результаты моделирования показывают эффективность предложенного метода, особенно в отношении отсутствия вибрации, реакции на внезапные изменения нагрузки и устойчивости. Все расчеты для вышеуказанной работы были выполнены с использованием MATLAB/Simulink. Различные расчетные исследования дали весьма удовлетворительные результаты, и мы успешно улучшили потоки реальной и реактивной мощности на линии электропередачи, а также регулирование напряжения на шине, к которой она подключена, что позволяет изучить и проиллюстрировать эффективность и возможности UPFC для увеличения мощности

    A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

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    © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

    A high-precision current-mode WTA-MAX circuit with multichip capability

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    This paper presents a circuit design technique suitable for the realization of winner-take-all (WTA), maximum (MAX), looser-take-all (LTA), and minimum (MIN) circuits. The technique presented is based on current replication and comparison. Traditional techniques rely on the matching of an N transistors array, where N is the number of system inputs. This implies that when N increases, as the size of the circuit and the distance between transistors will also increase, transistor matching degradation and loss of precision in the overall system performance will result. Furthermore, when multichip systems are required, the transistor matching is even worse and performance is drastically degraded. The technique presented in this paper does not rely on the proper matching of N transistors, but on the precise replication and comparison of currents. This can be performed by current mirrors with a limited number of outputs. Thus, N can increase without degrading the precision, even if the system is distributed among several chips. Also, the different chips constituting the system can be of different foundries without degrading the overall system precision. Experimental results that attest these facts are presented

    Fast synchronization 3R burst-mode receivers for passive optical networks

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    This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed
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