Modified Level Restorers Using Current Sink and Current Source Inverter Structures for BBL-PT Full Adder

Full adder is an essential component for the design and development of all types of processors like digital signal processors (DSP), microprocessors etc. In most of these systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is a significant goal. In this paper, we proposed two modified level restorers using current sink and current source inverter structures for branch-based logic and pass-transistor (BBL-PT) full adder [1]. In BBL-PT full adder, there lies a drawback i.e. voltage step existence that could be eliminated in the proposed logics by using the current sink inverter and current source inverter structures. The proposed full adders are compared with the two standard and well-known logic styles, i.e. conventional static CMOS logic and Complementary Pass transistor Logic (CPL), demonstrated the good delay performance. The implementation of 8-bit ripple carry adder based on proposed full adders are finally demonstrated. The CPL 8-bit RCA and as well as the proposed ones is having better delay performance than the static CMOS and BBL-PT 8-bit RCA. The performance of the proposed BBL-PT cell with current sink & current source inverter structures are examined using PSPICE and the model parameters of a 0.13 µm CMOS process

CMOS VLSI correlator design for radio-astronomical signal processing : a thesis presented in partial fulfilment of the requirements for the degree of Doctor of Philosophy in Engineering at Massey University, Auckland, New Zealand

Multi-element radio telescopes employ methods of indirect imaging to capture the image of the sky. These methods are in contrast to direct imaging methods whereby the image is constructed from sensor measurements directly and involve extensive signal processing on antenna signals. The Square Kilometre Array, or the SKA, is a future radio telescope of this type that, once built, will become the largest telescope in the world. The unprecedented scale of the SKA requires novel solutions to be developed for its signal processing pipeline one of the most resource-consuming parts of which is the correlator. The SKA uses the FX correlator construction that consists of two parts: the F part that translates antenna signals into frequency domain and the X part that cross-correlates these signals between each other. This research focuses on the integrated circuit design and VLSI implementation issues of the X part of a very large FX correlator in 28 nm and 130 nm CMOS. The correlator’s main processing operation is the complex multiply-accumulation (CMAC) for which custom 28 nm CMAC designs are presented and evaluated. Performance of various memories inside the correlator also affects overall efficiency, and input-buffered and output-buffered approaches are considered with the goal of improving upon it. For output-buffered designs, custom memory control circuits have been designed and prototyped in 130 nm that improve upon eDRAM by taking advantage of sequential access patterns. For the input-buffered architecture, a new scheme is proposed that decreases the usage of the input-buffer memory by a third by making use of multiple accumulators in every CMAC. Because cross-correlation is a very data-intensive process, high-performance SerDes I/O is essential to any practical ASIC implementation. On the I/O design, the 28 nm full-rate transmitter delivering 15 Gbps per lane is presented. This design consists of the scrambler, the serialiser, the digital VCO with analog fine-tuning and the SST driver including features of a 4-tap FFE, impedance tuning and amplitude tuning

Hand-arm vibration disorder among grass-cutter workers in Malaysia

Prolonged exposure to hand-transmitted vibration from grass-cutting machines has been associated with increasing occurrences of symptoms and signs of occupational diseases related to hand-arm vibration syndrome (HAVS). Methods. A cross-sectional study was carried out using an adopted HAVS questionnaire on hand-arm vibration exposure and symptoms distributed to 168 male workers from the grass and turf maintenance industry who use hand-held grass-cutting machines as part of their work. The prevalence ratio and symptom correlation to HAVS between high and low–moderate exposure risk groups were evaluated. Results. There were positive HAVS symptoms relationships between the low–moderate exposure group and the high exposure group among hand-held grass-cutting workers. The prevalence ratio was considered high because there were indicators that fingers turned white and felt numb, 3.63, 95% CI [1.41, 9.39] and 4.24, 95% CI [2.18, 8.27], respectively. Less than 14.3% of workers stated that they were aware of the occupational hand-arm vibration, and it seemed to be related to the finger blanching and numbness. Conclusion. The results suggest that HAVS is under-diagnosed in Malaysia, especially in the agricultural sectors. More information related to safety and health awareness programmes for HAVS exposure is required among hand-held grass-cutting workers

MADX: Memristors-As-Drivers for Crossbar logic

Memristors have the potential to not only replace conventional memory, but also to open up new design possibilities because they store 1s and 0s as resistances rather than voltages. A memristor architecture that has attracted interest for its versatility and ease of integration with existing CMOS technologies is the crossbar array. In this paper, I modify the MAD scheme to create the MADX scheme for performing basic logic operations within a crossbar array. Then, I compare this scheme against two of the most well-known schemes, MAGIC and IMPLY. In the case study of a full-adder, both a one-bit and an 8-bit version, the MADX scheme achieves lower latency and substantially lower area requirements than both MAGIC and IMPLY. This is because it is more flexible about storing output values than either, does not destroy input values unlike IMPLY, and has more basic operations. In particular, it has XOR, which neither IMPLY nor MAGIC have and is useful for additionPlan II Honors Progra

Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

In this paper a new full adder is proposed The number of Transistors used in the proposed full adder is 13 Average leakage is 62 of conventional 28 transistor CMOS full adder The leakage power reduction results in overall power reduction The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tool

Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns.  Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT- design applications