44 research outputs found

    Realizing a CMOS RF Transceiver for Wireless Sensor Networks

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    Current reuse topology in UWB CMOS LNA

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    Design of frequency synthesizers for short range wireless transceivers

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    The rapid growth of the market for short-range wireless devices, with standards such as Bluetooth and Wireless LAN (IEEE 802.11) being the most important, has created a need for highly integrated transceivers that target drastic power and area reduction while providing a high level of integration. The radio section of the devices designed to establish communications using these standards is the limiting factor for the power reduction efforts. A key building block in a transceiver is the frequency synthesizer, since it operates at the highest frequency of the system and consumes a very large portion of the total power in the radio. This dissertation presents the basic theory and a design methodology of frequency synthesizers targeted for short-range wireless applications. Three different examples of synthesizers are presented. First a frequency synthesizer integrated in a Bluetooth receiver fabricated in 0.35μm CMOS technology. The receiver uses a low-IF architecture to downconvert the incoming Bluetooth signal to 2MHz. The second synthesizer is integrated within a dual-mode receiver capable of processing signals of the Bluetooth and Wireless LAN (IEEE 802.11b) standards. It is implemented in BiCMOS technology and operates the voltage controlled oscillator at twice the required frequency to generate quadrature signals through a divide-by-two circuit. A phase switching prescaler is featured in the synthesizer. A large capacitance is integrated on-chip using a capacitance multiplier circuit that provides a drastic area reduction while adding a negligible phase noise contribution. The third synthesizer is an extension of the second example. The operation range of the VCO is extended to cover a frequency band from 4.8GHz to 5.85GHz. By doing this, the synthesizer is capable of generating LO signals for Bluetooth and IEEE 802.11a, b and g standards. The quadrature output of the 5 - 6 GHz signal is generated through a first order RC - CR network with an automatic calibration loop. The loop uses a high frequency phase detector to measure the deviation from the 90° separation between the I and Q branches and implements an algorithm to minimize the phase errors between the I and Q branches and their differential counterparts

    Low-power CMOS front-ends for wireless personal area networks

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    The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.Ph.D.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanoui

    CMOS Low-Noise Amplifier Design for Reconfigurable Mobile Terminals

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    Kommunikationsstandards aus Europa, Japan und den USA sind mit einander nicht kompatibel. Das ist einen Nachteil besonders in der Mobiltelefonie, wo es bisher keinen allgemeinen Standard gibt. Die Vielzahl an Funkstandards führt zu einigen Nachteilen, deshalb scheint das Bedürfnis für Rekonfigurierbarkeit offensichtlich zu sein. Ein rekonfigurierbares Terminal sollte im Stande sein, verschiedene Standards zu unterstützen. Die vernünftige Integration von verschiedenen Standards kann Standards einschließen, die derselben Familie (z.B. GSM) gehören, aber in verschiedenen Kontinenten entwickelt werden. Solche Terminals existieren bereits und ein breites Angebot besteht auf dem Markt. Ein ziemlich neuer Ansatz der Standardintegration ist die Kombination von verschiedenen Familien von Standards, zum Beispiel zwischen drahtloser Datenübertragung wie UMTS mit WLAN oder HIPERLAN. In diesem Fall sind fast alle Parameter, die einen Standard definieren, verschieden. In dieser Arbeit wird ein rekonfigurierbares Multistandard Terminal betrachtet, das sowohl OFDM basierte WLAN Standards (IEEE802.11 und Hiperlan/2) als auch den CDMA basierten UMTS FDD unterstützt. Besondere Aufmerksamkeit galt dem Empfänger dieses Terminals. Eine rekonfigurierbare hybride Architektur ist ausstelle einer Architektur entwickelt worden, die mehrere Parallele umschaltbare Sender-Empfänger verwendet. Zusätzlich zur hybriden Architektur werden die negativen Einflüsse des HF-Teils auf die Empfänger-Performance untersucht. Der zweite Teil dieser Arbeit behandelt Transistor-Physik und den Entwurf eines rauscharmen Verstärkers für einen rekonfigurierbaren Empfänger, wie oben beschrieben. Da die kleinen FET-Größen aktuellen submikrometer RF-MOS-Technologien niedrige Kapazitätswerte haben, sind große Induktivitäten für die Anpassung erforderlich. Wegen ihre großen Abmessungen werden sie außerhalb des ICs realisiert. Deshalb kann die Pad-Kapazität im Designprozess nicht länger vernachlässigt werden. Es wird gezeigt, dass die Rauschzahl von rauscharmen Verstärkern wesentlich durch die richtige Wahl von passiven Systemkomponenten verbessert werden kann. Eine Designmethodik wird eingeführt, die den equivalenten Rauschwiderstand reduziert, und dadurch sehr gutes Rauschverhalten trotz relativ schlechte Rauschanpassung erreichen kann. Die Messungen des Verstärkers hinsichtlich Rauschverhalten und Stromverbrauch, zeigen sehr gute Ergebnisse. Sie gehören zu den besten überhaupt bekannten. 0.76 dB-Rauschzahl und 12 dB Gewinn wurden bei 2.14 GHz erreicht, bei 3.5 mA Stromverbrauch und 1.2V Betriebsspannung.Communication standards developed in Europe, Japan and USA are not compatible with each other. This is a profound drawback particularly in the digital cellular telephony, where there is no common standard up to now. The variety of wireless standards leads to some disadvantages, therefore the need for reconfigurability seems to be evident. A reconfigurable terminal should be able to support different standards. Reasonable integration of different standards may include standards, which belong to the same family (e.g., GSM), but are developed in different continents. Such terminals have been already produced and a broad offer exists on the market. A rather new approach of the standard integration is the combination of different families of standards, for example between wireless data and digital cellular telephony like UMTS with WLAN or HIPERLAN. In this case, nearly all parameters defining a standard are different. In the scope of this work the multistandard, reconfigurable terminal is considered that supports the OFDM based WLAN standards (IEEE802.11 and Hiperlan/2) and the CDMA based UMTS FDD standard. Special consideration has been made for the receiver of this terminal. A reconfigurable hybrid architecture has been developed, rather than an architecture using many parallel switchable transceivers. Additionally to the hybrid architecture, a study on RF impairments is given. The second part of this work handles with transistor physics and low noise amplifier design for a reconfigurable receiver, defined earlier. Since the small FET sizes of state of the art sub-micron RF-MOS-technologies have low capacitance values, thus large inductors are needed for matching. Because of theirs large dimensions they are placed off-chip. For this reason, the pad capacitance can not be longer neglected in the design process. % It is shown that the noise figure of low-noise amplifiers can be improved considerably by a proper choice of passive components. A design methodology is introduced, which reduces the equivalent noise resistance, and thus very good noise performance can be achieved in spite of rather poor noise matching. The measurements of the amplifier, in respect to the noise performance and power consumption, show very good results, one of the best ever reported. 0.76 dB noise figure and 12 dB gain were achieved at 2.14~GHz, 3.5 mA supply current and 1.2 V supply voltage

    A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

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    © 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

    A New Application of Current Conveyors: The Design of Wideband Controllable Low-Noise Amplifiers

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    The aim of this paper is three-fold. First, it reviews the low-noise amplifier and its relevance in wireless communications receivers. Then it presents an exhaustive review of the existing topologies. Finally, it introduces a new class of LNAs, based on current conveyors, describing the founding principle and the performances of a new single-ended LNA. The new LNAs offer the following notable advantages: total absence of passive elements (and the smallest LNAs in their respective classes); wideband performance, with stable frequency responses from 0 to 3 GHz; easy gain control over wide ranges (0 to 20 dB). Comparisons with other topologies prove that the new class of LNA greatly advances the state of the art

    Design of low power CMOS UWB transceiver ICs

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