An Overview of the AURORA Gigabit Testbed

AURORA is one of five U.S. testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. AURORA is also an experiment in collaboration, where government support (through the Corporation for National Research Initiatives, which is in turn funded by DARPA and the NSF) has spurred interaction among centers of excellence in industry, academia, and government. The emphasis of the AURORA testbed, distinct from the other four testbeds, is research into the supporting technologies for gigabit networking. Our targets include new software architectures, network abstractions, hardware technologies, and applications. This paper provides an overview of the goals and methodologies employed in AURORA, and reports preliminary results from our first year of research

The AURORA Gigabit Testbed

AURORA is one of five U.S. networking testbeds charged with exploring applications of, and technologies necessary for, networks operating at gigabit per second or higher bandwidths. The emphasis of the AURORA testbed, distinct from the other four testbeds, BLANCA, CASA, NECTAR, and VISTANET, is research into the supporting technologies for gigabit networking. Like the other testbeds, AURORA itself is an experiment in collaboration, where government initiative (in the form of the Corporation for National Research Initiatives, which is funded by DARPA and the National Science Foundation) has spurred interaction among pre-existing centers of excellence in industry, academia, and government. AURORA has been charged with research into networking technologies that will underpin future high-speed networks. This paper provides an overview of the goals and methodologies employed in AURORA, and points to some preliminary results from our first year of research, ranging from analytic results to experimental prototype hardware. This paper enunciates our targets, which include new software architectures, network abstractions, and hardware technologies, as well as applications for our work

Low Cost Quality of Service Multicast Routing in High Speed Networks

Many of the services envisaged for high speed networks, such as B-ISDN/ATM, will support real-time applications with large numbers of users. Examples of these types of application range from those used by closed groups, such as private video meetings or conferences, where all participants must be known to the sender, to applications used by open groups, such as video lectures, where partcipants need not be known by the sender. These types of application will require high volumes of network resources in addition to the real-time delay constraints on data delivery. For these reasons, several multicast routing heuristics have been proposed to support both interactive and distribution multimedia services, in high speed networks. The objective of such heuristics is to minimise the multicast tree cost while maintaining a real-time bound on delay. Previous evaluation work has compared the relative average performance of some of these heuristics and concludes that they are generally efficient, although some perform better for small multicast groups and others perform better for larger groups. Firstly, we present a detailed analysis and evaluation of some of these heuristics which illustrates that in some situations their average performance is reversed; a heuristic that in general produces efficient solutions for small multicasts may sometimes produce a more efficient solution for a particular large multicast, in a specific network. Also, in a limited number of cases using Dijkstra's algorithm produces the best result. We conclude that the efficiency of a heuristic solution depends on the topology of both the network and the multicast, and that it is difficult to predict. Because of this unpredictability we propose the integration of two heuristics with Dijkstra's shortest path tree algorithm to produce a hybrid that consistently generates efficient multicast solutions for all possible multicast groups in any network. These heuristics are based on Dijkstra's algorithm which maintains acceptable time complexity for the hybrid, and they rarely produce inefficient solutions for the same network/multicast. The resulting performance attained is generally good and in the rare worst cases is that of the shortest path tree. The performance of our hybrid is supported by our evaluation results. Secondly, we examine the stability of multicast trees where multicast group membership is dynamic. We conclude that, in general, the more efficient the solution of a heuristic is, the less stable the multicast tree will be as multicast group membership changes. For this reason, while the hybrid solution we propose might be suitable for use with closed user group multicasts, which are likely to be stable, we need a different approach for open user group multicasting, where group membership may be highly volatile. We propose an extension to an existing heuristic that ensures multicast tree stability where multicast group membership is dynamic. Although this extension decreases the efficiency of the heuristics solutions, its performance is significantly better than that of the worst case, a shortest path tree. Finally, we consider how we might apply the hybrid and the extended heuristic in current and future multicast routing protocols for the Internet and for ATM Networks.

BMSN and SpiderNet as large scale ATM switch interconnection architectures.

by Kin-Yu Cheung.Thesis (M.Phil.)--Chinese University of Hong Kong, 1997.Includes bibliographical references (leaves 64-[68]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Multistage Interconnection Architectures --- p.2Chapter 1.2 --- Interconnection Topologies --- p.4Chapter 1.3 --- Design of Switch Module-An Example of Multichannel Switch --- p.7Chapter 1.4 --- Organization --- p.8Chapter 1.5 --- Publication --- p.9Chapter 2 --- BMSN and SpiderNet: Two Large Scale ATM Switches --- p.13Chapter 2.1 --- Introduction --- p.13Chapter 2.2 --- Architecture --- p.14Chapter 2.2.1 --- Topology --- p.14Chapter 2.2.2 --- Switch Modules --- p.15Chapter 2.3 --- Routing --- p.17Chapter 2.3.1 --- VP/VC Routing --- p.18Chapter 2.3.2 --- VP/VC Routing Control --- p.22Chapter 2.3.3 --- Cell Routing --- p.23Chapter 2.3.4 --- Alternate Path Routing for Fault Tolerance --- p.24Chapter 2.4 --- SpiderNet --- p.25Chapter 2.5 --- Performance and Discussion --- p.26Chapter 2.5.1 --- BMSN vs SpiderNet --- p.26Chapter 2.5.2 --- Network Capacity --- p.29Chapter 2.6 --- Concluding Remarks --- p.30Chapter 3 --- Multichannel ATM Switching --- p.39Chapter 3.1 --- Introduction --- p.39Chapter 3.2 --- Switch Design --- p.40Chapter 3.3 --- Channel Allocation Algorithms --- p.41Chapter 3.3.1 --- VC-Based String Round Robin (VCB-SRR) Algorithm --- p.41Chapter 3.3.2 --- Implementation of the VCB-SRR Algorithm --- p.43Chapter 3.3.3 --- Channel Group Based Round Robin (CGB-RR) Algorithm --- p.50Chapter 3.3.4 --- Implementation of the CGB-RR Algorithm --- p.51Chapter 3.4 --- Performance and Discussion --- p.53Chapter 3.5 --- Concluding Remarks --- p.57Chapter 4 --- Conclusion --- p.62Bibliography --- p.6

Multi Protocol Label Switching: Quality of Service, Traffic Engineering application, and Virtual Private Network application

This thesis discusses the QoS feature, Traffic Engineering (TE) application, and Virtual Private Network (VPN) application of the Multi Protocol Label Switching (MPLS) protocol. This thesis concentrates on comparing MPLS with other prominent technologies such as Internet Protocol (IP), Asynchronous Transfer Mode (ATM), and Frame Relay (FR). MPLS combines the flexibility of Internet Protocol (IP) with the connection oriented approach of Asynchronous Transfer Mode (ATM) or Frame Relay (FR). Section 1 lists several advantages MPLS brings over other technologies. Section 2 covers architecture and a brief description of the key components of MPLS. The information provided in Section 2 builds a background to compare MPLS with the other technologies in the rest of the sections. Since it is anticipate that MPLS will be a main core network technology, MPLS is required to work with two currently available QoS architectures: Integrated Service (IntServ) architecture and Differentiated Service (DiffServ) architecture. Even though the MPLS does not introduce a new QoS architecture or enhance the existing QoS architectures, it works seamlessly with both QoS architectures and provides proper QoS support to the customer. Section 3 provides the details of how MPLS supports various functions of the IntServ and DiffServ architectures. TE helps Internet Service Provider (ISP) optimize the use of available resources, minimize the operational costs, and maximize the revenues. MPLS provides efficient TE functions which prove to be superior to IP and ATM/FR. Section 4 discusses how MPLS supports the TE functionality and what makes MPLS superior to other competitive technologies. ATM and FR are still required as a backbone technology in some areas where converting the backbone to IP or MPLS does not make sense or customer demands simply require ATM or FR. In this case, it is important for MPLS to work with ATM and FR. Section 5 highlights the interoperability issues and solutions for MPLS while working in conjunction with ATM and FR. In section 6, various VPN tunnel types are discussed and compared with the MPLS VPN tunnel type. The MPLS VPN tunnel type is concluded as an optimal tunnel approach because it provides security, multiplexing, and the other important features that are reburied by the VPN customer and the ISP. Various MPLS layer 2 and layer 3 VPN solutions are also briefly discussed. In section 7 I conclude with the details of an actual implementation of a layer 3 MPLS VPN solution that works in conjunction with Border Gateway Protocol (BGP)

Software-defined Networking enabled Resource Management and Security Provisioning in 5G Heterogeneous Networks

Due to the explosive growth of mobile data traffic and the shortage of spectral resources, 5G networks are envisioned to have a densified heterogeneous network (HetNet) architecture, combining multiple radio access technologies (multi-RATs) into a single holistic network. The co-existing of multi-tier architectures bring new challenges, especially on resource management and security provisioning, due to the lack of common interface and consistent policy across HetNets. In this thesis, we aim to address the technical challenges of data traffic management, coordinated spectrum sharing and security provisioning in 5G HetNets through the introduction of a programmable management platform based on Software-defined networking (SDN). To address the spectrum shortage problem in cellular networks, cellular data traffic is efficiently offloaded to the Wi-Fi network, and the quality of service of user applications is guaranteed with the proposed delay tolerance based partial data offloading algorithm. A two-layered information collection is also applied to best load balancing decision-making. Numerical results show that the proposed schemes exploit an SDN controller\u27s global view of the HetNets and take optimized resource allocation decisions. To support growing vehicle-generated data traffic in 5G-vehicle ad hoc networks (VANET), SDN-enabled adaptive vehicle clustering algorithm is proposed based on the real-time road traffic condition collected from HetNet infrastructure. Traffic offloading is achieved within each cluster and dynamic beamformed transmission is also applied to improve trunk link communication quality. To further achieve a coordinated spectrum sharing across HetNets, an SDN enabled orchestrated spectrum sharing scheme that integrates participating HetNets into an amalgamated network through a common configuration interface and real-time information exchange is proposed. In order to effectively protect incumbent users, a real-time 3D interference map is developed to guide the spectrum access based on the SDN global view. MATLAB simulations confirm that average interference at incumbents is reduced as well as the average number of denied access. Moreover, to tackle the contradiction between more stringent latency requirement of 5G and the potential delay induced by frequent authentications in 5G small cells and HetNets, an SDN-enabled fast authentication scheme is proposed in this thesis to simplify authentication handover, through sharing of user-dependent secure context information (SCI) among related access points. The proposed SCI is a weighted combination of user-specific attributes, which provides unique fingerprint of the specific device without additional hardware and computation cost. Numerical results show that the proposed non-cryptographic authentication scheme achieves comparable security with traditional cryptographic algorithms, while reduces authentication complexity and latency especially when network load is high

Multicast cross-path ATM switches: principles, designs and performance evaluations.

by Lin Hon Man.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 59-[63]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Organization of Thesis --- p.3Chapter 2 --- Principles of Multicast Cross-Path Switches --- p.4Chapter 2.1 --- Introduction --- p.4Chapter 2.2 --- Unicast Cross-Path switch --- p.5Chapter 2.2.1 --- Routing properties in Clos networks --- p.5Chapter 2.2.2 --- Quasi-static routing procedures --- p.5Chapter 2.2.3 --- Capacity and Route Assignment --- p.7Chapter 2.3 --- Multicast Cross-Path Switch --- p.8Chapter 2.3.1 --- Scheme 1 - Cell replication performed at both input and output stages --- p.10Chapter 2.3.2 --- Scheme 2 - Cell replication performed only at the input stage --- p.10Chapter 3 --- Architectures --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Input Module Design (Scheme 1) --- p.16Chapter 3.2.1 --- Input Header Translator --- p.16Chapter 3.2.2 --- Input Module Controller --- p.17Chapter 3.2.3 --- Input Replication Network (Scheme 1) --- p.19Chapter 3.2.4 --- Routing Network --- p.23Chapter 3.3 --- Central Modules --- p.24Chapter 3.4 --- Output Module Design (Scheme 1) --- p.24Chapter 3.5 --- Input Module Design (Scheme 2) --- p.25Chapter 3.5.1 --- Input Header Translator (Scheme 2) --- p.26Chapter 3.5.2 --- Input Module Controller (Scheme 2) --- p.27Chapter 3.5.3 --- Input Replication Network (Scheme 2) --- p.28Chapter 3.6 --- Output Module Design (Scheme 2) --- p.29Chapter 4 --- Performance Evaluations --- p.31Chapter 4.1 --- Introduction --- p.31Chapter 4.2 --- Traffic characteristics --- p.31Chapter 4.2.1 --- Fanout distribution --- p.31Chapter 4.2.2 --- Middle stage traffic load and its calculation --- p.32Chapter 4.3 --- Throughput Performance --- p.34Chapter 4.4 --- Delay Performance --- p.37Chapter 4.4.1 --- Input Stage Delay --- p.38Chapter 4.4.2 --- Output Stage Delay --- p.39Chapter 4.5 --- Cell Loss Performance --- p.43Chapter 4.5.1 --- Cell Loss due to Buffer Overflow --- p.44Chapter 4.5.2 --- Cell Loss Due to Output Contention --- p.45Chapter 4.6 --- Complexities --- p.50Chapter 5 --- Conclusions --- p.57Bibliography --- p.5

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance