Design and Test of a Gate Driver with Variable Drive and Self-Test Capability Implemented in a Silicon Carbide CMOS Process

Discrete silicon carbide (SiC) power devices have long demonstrated abilities that outpace those of standard silicon (Si) parts. The improved physical characteristics allow for faster switching, lower on-resistance, and temperature performance. The capabilities unleashed by these devices allow for higher efficiency switch-mode converters as well as the advance of power electronics into new high-temperature regimes previously unimaginable with silicon devices. While SiC power devices have reached a relative level of maturity, recent work has pushed the temperature boundaries of control electronics further with silicon carbide integrated circuits. The primary requirement to ensure rapid switching of power MOSFETs was a gate drive buffer capable of taking a control signal and driving the MOSFET gate with high current required. In this work, the first integrated SiC CMOS gate driver was developed in a 1.2 μm SiC CMOS process to drive a SiC power MOSFET. The driver was designed for close integration inside a power module and exposure to high temperatures. The drive strength of the gate driver was controllable to allow for managing power MOSFET switching speed and potential drain voltage overshoot. Output transistor layouts were optimized using custom Python software in conjunction with existing design tool resources. A wafer-level test system was developed to identify yield issues in the gate driver output transistors. This method allowed for qualitative and quantitative evaluation of transistor leakage while the system was under probe. Wafer-level testing and results are presented. The gate driver was tested under high temperature operation up to 530 degrees celsius. An integrated module was built and tested to illustrate the capability of the gate driver to control a power MOSFET under load. The adjustable drive strength feature was successfully demonstrated

Design of an Advanced Programmable Current-Source Gate Driver for Dynamic Control of SiC Device

Silicon carbide (SiC) power devices outperform Silicon-based devices in operational voltage levels, power densities, operational temperatures and switching frequencies. However, the gate oxide of SiC-based device is more fragile compared with its Si counterpart. The vulnerability of the gate oxide in SiC power devices requires the development of a gate driver that is able to have more control during the turn-on and turn-off process. This paper proposes an innovative current-source gate driver where the gate current can be fully programmed. The novelty of the gate driver is that the dynamic switching transients and the static on/off-state can be controlled independently. In order to achieve this approach, a signal decomposition and reconstruction technique is proposed to apply the separate control over the dynamic switching transient and the static on/off-state gate voltage respectively. The fundamental principle of the proposed circuit is verified in simulation. In addition, a prototype of the active gate driver has been built and tested to validate the effectiveness of the flexible control over the gate voltage

Phase substitution of spare converter for a failed one of parallel phase staggered converters

Failure detection and substitution of a spare module is provided in a system having a plurality of phase staggered modules connected in parallel to deliver regulated voltage from an unregulated source. Phase control signals applied to the active converter modules are applied to the spare module through NOR gates associated with and disabled by the power output of respective modules such that failure of any one enables its phase control signal to be applied to the spare module, thus controlling the spare module to operate in the phase position of the failed module. A NAND gate detects when any one active module fails and enables a gate in the spare module, thus activating the spare module

NEW GENERATION OF 3.3 KV IGBTS WITH MONOLITICALLY INTEGRATED VOLTAGE AND CURRENT SENSORS

Although IGBT modules are widely used as power semiconductor switch in many high power applications, there are still reliability problems related to the current unbalance between paralleled IGBTs that may destroy the whole module and, eventually, the power system. Indeed, short-circuit and overvoltage events can also destroy some of the IGBTs of the power module. In this sense, the instantaneous monitoring of the anode current and voltage values and the use of a more intelligent gate driver able to work with the signals of each particular IGBT of the module would enhance its operating lifetime. In this sense, the paper describes the design, optimization, fabrication and basic performances of 3.3 kV – 50 A punch-through IGBTs for traction and tap changer applications where anode current and voltage sensors are monolithically integrated within the IGBT core

Development and performance of pulse-width-modulated static inverter and converter modules

Pulse-width-modulated inverter and converter modules are being developed for modular aerospace electrical power systems. The modules, rate 2.5 kilowatts per module and 10-minute - 150-percent overload, operate from 56 volts dc. The converter module provides two output voltages: a nominal link voltage of 200 volts dc when used with the inverter, and 150 volts dc to a load bus when used separately. The inverter module output is 400-hertz, sinusoidal, three-phase, 120/208 volts. Tests of breadboard models with standard parts and integrated circuits show rated power efficiencies of 71.4 and 85.1 percent and voltage regulation of 5 and 3.1 percent for inverter and converter modules, respectively. Sine-wave output distortion is 0.74 percent

Airborne transistorized telemeter system model sst-i

Airborne transistorized telemeter system Mode SST-1 for small sounding rocket

Preliminary Investigation of a Waveform Analysis with the WASA and the ACQIRIS Readout Electronics

The Group for the development of neutron and gamma detectors in the Central Institute of Engineering, Electronics and Analytics (ZEA-2) at Forschungszentrum J\"ulich (FZJ) is developing a fast Anger Camera prototype for improving the rejection of the gamma contamination during the detection of neutrons. The prototype is based on a scintillating plate for neutron capture and on the subsequent generation of scintillating light collected by a matrix of 4x4 vacuum Photomultipliers R268 by Hamamatsu. According to the impinging point position of the incoming neutrons the light is collected by different PMTs, and via dedicated algorithms the x and y coordinates can be calculated. In this note the WASA and ACQIRIS readout electronics are compared while performing a waveform analysis of the signals generated by using both an analogue pulse generator and an LED+PMT system. Different options of pre-amplifiers and amplifiers are considered, and the results are here presented and commented. At this stage of the prototype development, systematical studies were not performed while the scope of this work was only to validate the principle of operations by using both readout systems.Comment: 36 Pages. The current version V1.1 has minor typos correcte

Design of a Broadband Amplifier for High Speed Applications

This paper provides comprehensive insight into the design approach followed for an amplifier dedicated to high speed base band signals. To demonstrate the methodology, an amplifier consisting of nine PHEMT cascode cells within a distributed amplifier topology was designed. The resulting frequency response is 40 GHz at the 3-dB point, and the output voltage for a 43 Gbps eye diagram is 7.3 Vpp at the chip terminal

First functionality tests of a 64 x 64 pixel DSSC sensor module connected to the complete ladder readout

The European X-ray Free Electron Laser (XFEL.EU) will provide every 0.1 s a train of 2700 spatially coherent ultrashort X-ray pulses at 4.5 MHz repetition rate. The Small Quantum Systems (SQS) instrument and the Spectroscopy and Coherent Scattering instrument (SCS) operate with soft X-rays between 0.5 keV - 6keV. The DEPFET Sensor with Signal Compression (DSSC) detector is being developed to meet the requirements set by these two XFEL.EU instruments. The DSSC imager is a 1 mega-pixel camera able to store up to 800 single-pulse images per train. The so-called ladder is the basic unit of the DSSC detector. It is the single unit out of sixteen identical-units composing the DSSC-megapixel camera, containing all representative electronic components of the full-size system and allows testing the full electronic chain. Each DSSC ladder has a focal plane sensor with 128 x 512 pixels. The read-out ASIC provides full-parallel readout of the sensor pixels. Every read-out channel contains an amplifier and an analog filter, an up-to 9 bit ADC and the digital memory. The ASIC amplifier have a double front-end to allow one to use either DEPFET sensors or Mini-SDD sensors. In the first case, the signal compression is a characteristic intrinsic of the sensor; in the second case, the compression is implemented at the first amplification stage. The goal of signal compression is to meet the requirement of single-photon detection capability and wide dynamic range. We present the first results of measurements obtained using a 64 x 64 pixel DEPFET sensor attached to the full final electronic and data-acquisition chain.Comment: Preprint proceeding for IWORID 2016, 18th International Workshop on Radiation Imaging Detectors, 3rd-7th July 2016, Barcelona, Spai