CIRCUIT MODULES FOR SIX-PORT REFLECTOMETER ON CHIP

Broadband signal generator is an indispensable module for broadband Six-Port Reflectometer (SPR). To integrate a whole SPR system on a chip, the source must be compact. In this thesis, a three-stage voltage-controlled oscillator (VCO), using two parallel weak invertor-chain oscillators and sense amplifiers, is proposed and designed in a 0.13 µm CMOS process. These two parallel weak inverter-chain oscillators extend the low frequency operating range and the sense amplifiers expand the high frequency operation. The measurement results show that the oscillator can be tuned from 430 MHz to 12 GHz, which satisfies the targeted SPR operating frequency range. In order to expand the operating frequency band of the SPR, an introduction of the tuning mechanisms is necessary. Inductors and capacitors are the two basic components for the circuit modules of an SPR. Varactors are provided by process vendors. In this thesis, a novel differential active inductor is proposed and implemented in a 0.13 µm CMOS process. The measured self-resonance frequency is 6 GHz, which is the highest self-resonance frequency published thus far for a differential inductor. The proposed structure is further improved by adding a symmetrical negative resistor. Post layout shows a 10 GHz self-resonance frequency. A power divider is a common module in the SPR and microwave circuits. A new lumped-element power divider structure, which presents the strongest tolerance to parasitic resistors in capacitors and inductors, is proposed and analyzed in this thesis by even- and odd-mode method. Varactors and the above-mentioned active inductors are used to build the proposed power divider. The circuit is designed in 0.13 µm CMOS technology with a core area of 300 µm_265 µm. Post layout simulation yields a tuning range from 1 GHz to 7.5 GHz

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Microwave and Millimeter-Wave Multi-Band Power Amplifiers, Power Combining Networks, and Transmitter Front-End in Silicon Germanium BiCMOS Technology

This dissertation presents new circuit architectures and techniques for designing high performance microwave and millimeter-wave circuits using 0.18-µm SiGe BiCMOS process for advanced wireless communication and sensing systems. The high performance single- and multi-band power amplifiers working in microwave and millimeter-wave frequency ranges are proposed. A 10-19, 23-39, and 33-40 GHz concurrent tri-band power amplifier in the respective Ku-, K-, and Ka-band using the distributed amplifier structure is presented first. Instead of utilizing multi-band matching networks, this amplifier is realized based on distributed amplifier structure and two active notch filters employed at each gain cell to form tri-band response. In addition, a power amplifier operating across the entire K-band is proposed. By employing lumped-element Wilkinson power divider and combiner, it produces high output power, high gain, and power added efficiency characteristics over broadband due to its inherent low-pass filtering response. Moreover, a highly integrated V-band power amplifier is presented. This power amplifier consists of four medium unit power cells combined with a four-way parallel power combining network. Secondly, microwave and millimeter-wave power combining and dividing networks are proposed. A wideband power divider and combiner operating up to 67 GHz is developed by adopting capacitive loading slow-wave transmission line to reduce size as well as insertion loss. Also, two-way and 16-way 24/60 GHz dual-band power divider networks in the K/V-band are proposed. The two-way dual-band power divider is realized with a slow-wave transmission line and two shunt connected LC resonators in order to minimize the chip size as well as insertion loss. Furthermore, a 16-way dual-band power dividing and combining network is developed for a dual-band 24/60 GHz 4×4 array system. This network incorporates a two-way dual-band power divider, lumped-element based Wilkinson power dividers, and multi-section transmission line based Wilkinson structures. Finally, a K-/V-band dual-band transmitter front-end is proposed. To realize the transmitter, a diplexer with good diplexing performance and K- and V-band variable gain amplifiers having low phase variation with gain tuning are designed. The transmitter is integrated with two diplexers, K- and V-band variable gain amplifiers, and two power amplifiers resulting in high gain, high output power, and low-phase variation with all gain control stages

Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX

Wideband Circuits and Antenna Designs for mm-Wave/5G Phased Arrays

The objective of this work is to present the performance and feasibility of wideband circuits and antennas for future mm-Wave phased array systems. Chapter 1 introduces the motivation of this research, first explaining the desire to operate at higher frequency regimes. Then focus is directed on the rich application spaces at mm-Wave frequencies and the corresponding need for wideband, compact, and fully integrated system-on-chip (SoC) solutions. A brief study of advanced node commercial silicon processes is also examined to demonstrate the increasing feasibility of implementing the aforementioned SoC solutions on silicon. Chapter 2 presents a design methodology of a novel ultra-compact, low-loss, and wideband mm-Wave Wilkinson Power Divider (WPD). Careful study and analysis reveal optimal and necessary design parameters and equations in terms of the coupling and mutual inductances within the structure, yielding a device that is competitive with existing literature. Chapter 3 first introduces the operation principle of spiral antennas (SA). The unique properties of SAs that make them great candidates for use in future mm-Wave phased arrays are explored. The rest of this chapter discusses the design, analysis, and results of an octagonal 4-arm Archimedean SA. Lastly, Chapter 4 provides closing remarks and discusses potential future work.M.S

A survey on RF and microwave doherty power amplifier for mobile handset applications

This survey addresses the cutting-edge load modulation microwave and radio frequency power amplifiers for next-generation wireless communication standards. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. Moreover, advance design architectures for enhancing the Doherty power amplifier’s performance in terms of higher efficiency and wider bandwidth characteristics, as well as the compact design techniques of Doherty amplifier that meets the requirements of legacy 5G handset applications, will be discussed.Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-RFundação para a Ciência e a Tecnologia | Ref. UIDP/50008/201

Broadband phase shifter design for phased array radar systems

Ph.DDOCTOR OF PHILOSOPH

Efficient, High power Precision RF and mmWave Digital Transmitter Architectures

Digital transmitters offer several advantages over conventional analog transmitters such as reconfigurability, elimination of scaling-unfriendly, power hungry and bulky analog blocks and portability across technology. The rapid advancement of technology in CMOS processes also enables integration of complex digital signal processing circuitry on the same die as the digital transmitter to compensate for their non-idealities. The use of this digital assistance can, for instance, enable the use of highly efficient but nonlinear switching-class power amplifiers by compensating for their severe nonlinearity through digital predistortion. While this shift to digitally intensive transmitter architectures is propelled by the benefits stated above, several pressing challenges arise that vary in their nature depending on the frequency of operation - from RF to mmWave. Millimeter wave CMOS power amplifiers have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear power amplifiers with high efficiency under back-off. However, linearity and high efficiency are traditionally at odds with each other in conventional power amplifier design. In this dissertation, digital assistance is used to relax this trade-off and enable the use of state-of-the-art switching class power amplifiers. A novel digital transmitter architecture which simultaneously employs aggressive device-stacking and large-scale power combining for watt-class output power, dynamic load modulation for linearization, and improved efficiency under back-off by supply-switching and load modulation is presented. At RF frequencies, while the problem of watt-class power amplification has been long solved, more pressing challenges arise from the crowded spectrum in this regime. A major drawback of digital transmitters is the absence of a reconstruction filter after digital-to-analog conversion which causes the baseband quantization noise to get upconverted to RF and amplified at the output of the transmitter. In high power transmitters, this upconverted noise can be so strong as to prevent their use in FDD systems due to receiver desensitization or impose stringent coexistence challenges. In this dissertation, new quantization noise suppression techniques are presented which, for the first time, contribute toward making watt-class fully-integrated digital RF transmitters a viable alternative for FDD and coexistence scenarios. Specifically, the techniques involve embedding a mixed-domain multi-tap FIR filter within highly-efficient watt-class switching power amplifiers to suppress quantization noise, enhancing the bandwidth of noise suppression, enabling tunable location of suppression and overcoming the limitations of purely digital-domain filtering techniques for quantization noise

Design of Fully-Integrated High-Resolution Radars in CMOS and BiCMOS Technologies

The RADAR, acronym that stands for RAdio Detection And ranging, is a device that uses electromagnetic waves to detect the presence and the distance of an illuminated target. The idea of such a system was presented in the early 1900s to determine the presence of ships. Later on, with the approach of World War II, the radar gained the interest of the army who decided to use it for defense purposes, in order to detect the presence, the distance and the speed of ships, planes and even tanks. Nowadays, the use of similar systems is extended outside the military area. Common applications span from weather surveillance to Earth composition mapping and from flight control to vehicle speed monitoring. Moreover, the introduction of new ultrawideband (UWB) technologies makes it possible to perform radar imaging which can be successfully used in the automotive or medical field. The existence of a plenty of known applications is the reason behind the choice of the topic of this thesis, which is the design of fully-integrated high-resolution radars. The first part of this work gives a brief introduction on high resolution radars and describes its working principle in a mathematical way. Then it gives a comparison between the existing radar types and motivates the choice of an integrated solution instead of a discrete one. The second part concerns the analysis and design of two CMOS high-resolution radar prototypes tailored for the early detection of the breast cancer. This part begins with an explanation of the motivations behind this project. Then it gives a thorough system analysis which indicates the best radar architecture in presence of impairments and dictates all the electrical system specifications. Afterwards, it describes in depth each block of the transceivers with particular emphasis on the local oscillator (LO) generation system which is the most critical block of the designs. Finally, the last section of this part presents the measurement results. In particular, it shows that the designed radar operates over 3 octaves from 2 to 16GHz, has a conversion gain of 36dB, a flicker-noise-corner of 30Hz and a dynamic range of 107dB. These characteristics turn into a resolution of 3mm inside the body, more than enough to detect even the smallest tumor. The third and last part of this thesis focuses on the analysis and design of some important building blocks for phased-array radars, including phase shifter (PHS), true time delay (TTD) and power combiner. This part begins with an exhaustive introduction on phased array systems followed by a detailed description of each proposed lumped-element block. The main features of each block is the very low insertion loss, the wideband characteristic and the low area consumption. Finally, the major effects of circuit parasitics are described followed by simulation and measurement results

Architectures and Integrated Circuits for Efficient, High-power "Digital'' Transmitters for Millimeter-wave Applications

This thesis presents architectures and integrated circuits for the implementation of energy-efficient, high-power "digital'' transmitters to realize high-speed long-haul links at millimeter-wave frequencies in nano-scale silicon-based processes