Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU

In recent years, reversible logic has emerged as a promising computing paradigm having application in low power CMOS, quantum computing, nanotechnology, and optical computing. The classical set of gates such as AND, OR, and EXOR are not reversible. This paper utilizes a new 4 * 4 reversible gate called TSG gate to build the components of a primitive reversible/quantum ALU. The most significant aspect of the TSG gate is that it can work singly as a reversible full adder, that is reversible full adder can now be implemented with a single gate only. A Novel reversible 4:2 compressor is also designed from the TSG gate which is later used to design a novel 8x8 reversible Wallace tree multiplier. It is proved that the adder, 4:2 compressor and multiplier architectures designed using the TSG gate are better than their counterparts available in literature, in terms of number of reversible gates and garbage outputs. This is perhaps, the first attempt to design a reversible 4:2 compressor and a reversible Wallace tree multiplier as far as existing literature and our knowledge is concerned. Thus, this paper provides an initial threshold to build more complex systems which can execute complicated operations using reversible logic.Comment: 5 Pages; Published in Proceedings of the Fifth IEEE International Conference on Information, Communications and Signal Processing (ICICS 2005), Bangkok, Thailand, 6-9 December 2005,pp.1425-142

Design of Reversible Even and Odd Parity Generator and Checker Using Multifunctional Reversible Logic Gate (MRLG)

Digital data transmission made more efficient of communication. For error free transmission in the digital communication at the source end used parity generator and at destination used parity checker. This paper proposed design of 3 bit reversible Even and Odd parity generator and checker using the multifunctional reversible logic gate (MRLG). The proposed design is designed and simulated using cadence software

Design and synthesis of reversible logic

Energy lost during computation is an important issue for digital design. Today, all electronics devices suffer from energy lost due to the conventional logic system used. The amount of energy loss in the form of heat leads to immense challenges in nowadays circuit design. To overcome that, reversible logic has been invented. Since properties of reversible logic differ greatly than conventional logic, synthesis methods used for conventional logic cannot be used in reversible logic. In this dissertation, we proposed new synthesis algorithms and several circuit designs using reversible logic

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture

A New Reversible Design of Adder & Subtractor Using Reversible Logic Gates

Modern VLSI design circuitry is used for low power consumption which is the requirements of ICs. Reversible logic has its tremendous applications and importance because it doesn’t lose any single bit of information of no information while performing computation bit loss during computation; it reflects the result in low power dissipation. However, we have to convert the reversible circuits into fault tolerant reversible circuits; it helps to detect the occurrence of errors and faults. Parity preserving property can be used for this. A new parity preserving reversible gate is proposed in this paper, named as P2RG. The most significant aspect of this work is that it can work as a full adder as well as full subtractor by using one P2RG and Fredkin gate only. This proposed design is very good in terms of gate count, garbage outputs, constant inputs and area than the existing similitude. The concept behind the reversible logic circuits is that the inputs and outputs are same