66 research outputs found

    Recent Developments of Dual-Band Doherty Power Amplifiers for Upcoming Mobile Communications Systems

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    Power amplifiers in modern and future communications should be able to handle different modulation standards at different frequency bands, and in addition, to be compatible with the previous generations. This paper reviews the recent design techniques that have been used to operate dual-band amplifiers and in particular the Doherty amplifiers. Special attention is focused on the design methodologies used for power splitters, phase compensation networks, impedance inverter networks and impedance transformer networks of such power amplifier. The most important materials of the dual-band Doherty amplifier are highlighted and surveyed. The main problems and challenges covering dual-band design concepts are presented and discussed. In addition, improvement techniques to enhance such operations are also exploited. The study shows that the transistor parasitic has a great impact in the design of a dual-band amplifier, and reduction of the transforming ratio of the inverter simplifies the dual-band design. The offset line can be functionally replaced by a Π-network in dual-band design rather than T-network

    Concurrent Dual-band Doherty Power Amplifiers for Carrier Aggregation

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    Carrier aggregation is the main feature of the Long Term Evolution advanced (LTE-A) standard to increase the spectral efficiency and communication bandwidth. It calls for wireless transmitters to be multi-band and multi-standard to meet the demands of various deployment scenarios. In addition, these transmit radios must efficiently amplify signals characterized with a high peak-to-average power ratio (PAPR), which is caused by advanced modulation schemes. These two factors highlight the need for the multi-band Doherty power amplifier (DPA), which allows the transmitter remain in high efficiency at back-off power levels and maintain that high efficiency over multiple frequency bands. In this work, a novel output combining network is presented for the dual-band DPA design with extended fractional bandwidth for carrier aggregated signals. The proposed output combiner employs a modified Pi-shape network, which enables the absorption of output capacitances from both the main and peaking devices and eliminates the need for phase offset lines which are major sources of bandwidth limitation in the existing multiband DPAs. In addition to performing the impedance inversion, the proposed combiner incorporates the biasing feeds and presents small low-frequency impedances to both the main and peaking transistors. The inclusion of the bias feeds and small low low-frequency impedance feature improves the linearizability of the DPA when stimulated with concurrent dual-band modulated signals. Lastly, by using the gain contour at the back-off power level, the non-linear AM-AM response caused by the varying input capacitance of the main transistor is mitigated. The proposed dual-band output power combiner and the back-off gain contour technique were applied to design of a dual-band two-way Doherty PA using the commercialized 25W Gallium Nitride (GaN) transistor. Measurement of the two-way DPA shows a gain of 7.5- 9.5 dB at 2.05 - 2.3 GHz and 9 - 11 dB at 3.2 - 3.62 GHz. The efficiency at 6 dB back off is greater than 49% and 47% across the two frequency bands. The linearizability of the dual-band DPA is validated using various carrier aggregated signals. The PA exhibits linear behaviour when driven by up to 80 MHz intra-band carrier aggregated signal and 20 MHz concurrent dual-band signal after DPD. Additionally, carrier aggregated signals usually lead to a PAPR value between 8-10 dB. The efficiency of classic two-way DPA deteriorates when dealing with such signals. To cope with the efficiency deterioration, a three-way DPA was designed. Simulations of the three-way DPA show that the gain is greater than 9 dB within the two frequency bands, 2.05 - 2.32 GHz and 3.35 - 3.65 GHz. The efficiency at 10-dB back-off is greater than 40% in the two frequency bands

    High efficiency power amplifiers for modern mobile communications: The load-modulation approach

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    Modern mobile communication signals require power amplifiers able to maintain very high efficiency in a wide range of output power levels, which is a major issue for classical power amplifier architectures. Following the load-modulation approach, efficiency enhancement is achieved by dynamically changing the amplifier load impedance as a function of the input power. In this paper, a review of the widely-adopted Doherty power amplifier and of the other load-modulation efficiency enhancement techniques is presented. The main theoretical aspects behind each method are introduced, and the most relevant practical implementations available in recent literature are reported and discussed

    Linear Predistortion-less MIMO Transmitters

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    Broadband Power Amplifier Design with High Power, High Efficiency and Large Back-off Range

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    As modern communication system technology develops, the demand for devices with smaller size, higher efficiency, and larger bandwidth has increased dramatically. To achieve this purpose, a novel architecture of load modulated balanced amplifier (LMBA) with a unique load-modulation characteristic different from any existing LMBAs and Doherty power amplifiers (DPAs) was presented, which is named as Pseudo-Doherty LMBA (PD-LMBA). Based on a special combination of control amplifier (carrier) and balanced amplifier (peaking) together with proper phase and amplitude controls, an optimal load-modulation behavior can be achieved for PD-LMBA leading to maximized efficiency over extended power back-off range. More importantly, the efficiency optimization can be achieved with only a static setting of phase offset at a given frequency, which greatly simplifies the complexity for phase control. Furthermore, the co-operations of the carrier and peaking amplifiers in PD-LMBA are fully de-coupled, thus lifting the fundamental bandwidth barrier imposed on Doherty-based active load modulation. However, since PD-LMBA has CA over-driving concerns, a new load-modulated power amplifier (PA) architecture, Asymmetric Load-Modulated Balanced Amplifier (ALMBA), is proposed based on PD-LMBA. And a subsequent improved type-continuous mode Hybrid Asymmetric Load Modulation Balanced Amplifier (H-ALMBA) has been developed. The two sub-amplifiers (BA1 and BA2) of the balanced topology in an LMBA are set as peaking amplifiers with different thresholds when cooperating with the control amplifier (CA) as the carrier, forming a hybrid load modulation behavior between Doherty and ALMBA. Compared to standard LMBA, the proposed H-ALMBA has a three-way load modulation with CA, BA1 and BA2 through proper amplitude control and phase alignment. Thus, this new mode offers extended power back-off range and enhanced back-off efficiency without suffering from difficulty and complexity in wideband design as imposed on three-way Doherty PAs. Based on comprehensive theoretical derivation and analysis, the proposed H-ALMBA is designed and implemented using commercial GaN transistors and wideband quadrature couplers. Moreover, the continuous-mode matching is applied to the carrier amplifier achieving a maximized wideband efficiency at power back-off. This is the first time that continuous mode and ALMBA have been used in combination, and very satisfactory results have been achieved, exhibiting the highest 10-dB output power back-off (OBO) drain efficiency (DE) ever reported for wideband load-modulation PAs. The developed prototype experimentally demonstrates wide bandwidth from 0.55-2.2 GHz. The measurement exhibits an efficiency of 63-82% at peak output power, 51-62% for 5-dB OBO, and 50-66% for 10-dB OBO within the design bandwidth. When stimulated by a 20-MHz long term evolution (LTE) signal with 10.5-dB peak to average power ratio (PAPR), a 50-55% average efficiency is measured over the entire bandwidth at an average output power around 33 dBm

    Concurrent Multi-Band Envelope Tracking Power Amplifiers for Emerging Wireless Communications

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    Emerging wireless communication is shifting toward data-centric broadband services, resulting in employment of sophisticated and spectrum efficient modulation and access techniques. This yields communication signals with large peak-to-average power ratios (PAPR) and stringent linearity requirements. For example, future wireless communication standard, such as long term evolution advanced (LTE-A) require adoption of carrier aggregation techniques to improve their effective modulation bandwidth. The carrier aggregation technique for LTE-A incorporates multiple carriers over a wide frequency range to create a wider bandwidth of up to 100MHz. This will require future power amplifiers (PAs) and transmitters to efficiently amplify concurrent multi-band signals with large PAPR, while maintaining good linearity. Different back-off efficiency enhancement techniques are available, such as envelope tracking (ET) and Doherty. ET has gained a lot of attention recently as it can be applied to both base station and mobile transmitters. Unfortunately, few publications have investigated concurrent multi-band amplification using ET PAs, mainly due to the limited bandwidth of the envelope amplifier. In this thesis, a novel approach to enable concurrent amplification of multi-band signals using a single ET PA will be presented. This thesis begins by studying the sources of nonlinearities in single-band and dual-band PAs. Based on the analysis, a design methodology is proposed to reduce the sources of memory effects in single-band and dual-band PAs from the circuit design stage and improve their linearizability. Using the proposed design methodology, a 45W GaN PA was designed. The PA was linearized using easy to implement, memoryless digital pre-distortion (DPD) with 8 and 28 coefficients when driven with single-band and dual-band signals, respectively. This analysis and design methodology will enable the design of PAs with reduced memory effects, which can be linearized using simple, power efficient linearization techniques, such as lookup table or memoryless polynomial DPD. Note that the power dissipation of the linearization engine becomes crucial as we move toward smaller base station cells, such as femto- and pico-cells, where complicated DPD models cannot be implemented due to their significant power overhead. This analysis is also very important when implementing a multi-band ET PA system, where the sources of memory effects in the PA itself are minimized through the proposed design methodology. Next, the principle of concurrent dual-band ET operation using the low frequency component (LFC) of the envelope of the dual-band signal is presented. The proposed dual-band ET PA modulates the drain voltage of the PA using the LFC of the envelope of the dual-band signal. This will enable concurrent dual-band operation of the ET PA without posing extra bandwidth requirements on the envelope amplifier. A detailed efficiency and linearity analysis of the dual-band ET PA is also presented. Furthermore, a new dual-band DPD model with supply dependency is proposed in this thesis, capable of capturing and compensating for the sources of distortion in the dual-band ET PA. To the best of our knowledge, concurrent dual-band operation of ET PAs using the LFC of the envelope of the dual-band signal is presented for the first time in the literature. The proposed dual-band ET operation is validated using the measurement results of two GaN ET PA prototypes. Lastly, the principle of concurrent dual-band ET operation is extended to multi-band signals using the LFC of the envelope of the multi-band signal. The proposed multi-band ET operation is validated using the measurement results of a tri-band ET PA. To the best of our knowledge, this is the first reported tri-band ET PA in literature. The tri-band ET PA is linearized using a new tri-band DPD model with supply dependency

    Push-Pull Based High Efficiency and High Power Broadband Power Amplifiers for Wireless Base Stations

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    The monthly data throughput by 2021 is forecasted to be ten times that of December 2015. As a result of the on going dramatic increase in demand, service providers are assigned new frequency bands to accommodate more channels to carry more data. However, the usable part of the spectrum is a limited resource so modern communication signals were designed to be more spectrally efficient to send more bits over the same channel bandwidth. However, these spectrally efficient signals have high PAPR. The immediate reaction to these changes was to add additional RF front-end branches to accommodate the new frequency bands. Initially, the PAs used at the time were not optimized for back-off efficiency and where operating at low efficiency which caused significant increase in heat generation for the same average power produced which in turn increased cooling costs and reduced the life time of the PA. After the introduction of back-off efficiency enhancement techniques the PAs became more efficient however they were limited in bandwidth which is typically 10-15%. This work focuses on reducing the redundancy of power amplifiers in communication base stations while maintaining high back-off efficiency. After exploring the literature to understand the limitations of current implementations, it was found that the push-pull topology is often used at low frequency in broadband high power PAs. In the absence of a complimentary transistor pairs the push-pull implantation requires the use of balanced to unbalanced (balun) transformers. Various balun implantations were hence investigated to identify the most suitable option for broadband planar implementation. As a result, a methodology was proposed to co-design the balun and the matching network in order to have better control over the harmonic impedance. An 85 W push-pull PA was then designed based on the proposed methodology with a multi-octave bandwidth as a demonstration of the broadband potential of push-pull PAs at RF frequencies. Next, the two most popular techniques for back-off efficiency enhancement, i.e., ET and load modulation, were studied and the principle of load modulation was found to be more suitable for broadband signal transmission. The Doherty architecture is the most common implementation of load modulation and it comes in two basic variations, the PCL and SCL DPAs. The original architecture concepts are not only band limited but also ill-suited for high frequency designs where the transistors' parasitics introduce significant effect. However, later literature expanded on the original concept of the PCL variation which provided the needed flexibility for wider bandwidth implementations at a higher frequency. Using the broadband implementation and the co-design methodology two push-pull amplifiers were used in a PCL DPA topology and demonstrated that the push-pull utilization doesn't have a significant impact on the bandwidth of the output combiner as an octave bandwidth was achieved with the use of digital Doherty. Lastly, the thesis proposes a new approach for designing high power DPAs with extended bandwidth. It starts with a generic SCL DPA architecture to derive the equations that relate its underlying combiner's ABCD parameters to the transistor's optimum impedance and load impedance. These equations featured the possibility of significantly increasing the load impedance in SCL DPA compared to the one of the popular PCL DPA architecture. This is particularly beneficial when targeting very high power DPAs for macro-cell base stations and broadcast applications where very low load impedance can seriously complicate the design and limit the achievable bandwidth. To further maximize the load impedance increase, the proposed SCL DPA uses a push-pull topology for the main and peaking amplifier stages. A low-loss planar balanced to unbalanced transformer (balun) combiner network is then utilized to realize the SCL DPA combining. The proposed approach was finally applied to design a proof-of-concept 350 W SCL DPA which operates over the band spanning from 720 to 980 MHz. The prototype demonstrated a peak output power of about 55 dBm over a 30% FBW with a 6 dB back-off efficiency, measured using pulsed signal, between 46.6% and 54.6%. Furthermore, the modulated signal based measurement results confirmed the linearizability of the SCL DPA prototype while maintaining a back-off efficiency over 50% for a 7.1 dB peak to average power ratio signal

    Analysis and Design of CMOS Radio-Frequency Power Amplifiers

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    The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources

    Analysis and Design of CMOS Radio-Frequency Power Amplifiers

    Get PDF
    The continuous advancement of semiconductor technologies, especially CMOS technology, has enabled exponential growth of the wireless communication industry. This explosive growth in turn has completely changed people’s lives. The CMOS feature size scale down greatly benefits digital logic integrations, which result in more powerful, versatile, and economical digital signal processing. Further research and development has pushed analog, mixed-signal, and even radio-frequency (RF) circuit blocks to be implemented and integrated in CMOS. Future generations of wireless communication call for even further level of integration, and as of now, the only circuit block that is rarely integrated in CMOS along with other parts of the system is the power amplifier (PA). Due to the fact that the PA in a wireless communication system is the most power-hungry circuit block, the integration of RF PA in CMOS would potentially not only save the cost of the wireless communication system real estate, but also reduce power consumption since die-to-die connection loss can be eliminated. RF PA design involves handling large amounts of voltage and current at the radio frequencies, which in the present wireless communication standards are in the range of giga-hertz. Therefore, a good understanding of many aspects related to RF PA design is necessary. Theoretical analysis of the communication system, nonlinear effects of the PA, as well as the impedance matching network is systematically presented. The analysis of the nonlinear effects proposes a formal mathematical description of the multitone nonlinearity, and through its relationship with two-tone test, the proposed PA design methodology would greatly reduce the design time while improving the design accuracy. A thorough analysis of the available architecture and design techniques for efficiency and linearity enhancement of RF PA shows that despite tremendous amounts of research and development into this topic, the fundamental tradeoff between the two still limits the RF PA implementation largely within SiGe, GaAs, and InP technologies. A RF PA for Wideband Code-Division Multiple Access (WCDMA) application standard is proposed, designed, and implemented in CMOS that demonstrates the proposed segmentation technique that resolved the main tradeoff between power efficiency and linearity. The innovative architecture developed in this work is not limited to applications in the WCDMA communication protocol or the CMOS technology, although CMOS implementation would take advantage of the readily available digital resources
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