Switched capacitor networks : a novel prewarping procedure

Bibliography: leaves 152-157.Novel methods for prewarping filter specifications prior to realization. in Switched Capacitor (SC) form are presented. These allow the design of arbitrary response requirements, exhibiting a low amount of error that normally results from the frequency warping associated with sampled-data networks. Adjustment is applied to the pole and zero locations of a reference filter, using three distinct approaches (Center frequency "CF", Selectivity "S" and Complex Mapping "CM" pole/zero prewarping), developed for both the Lossless Discrete Integrator (LOI) and Bilinear (Bil) analog to digital transformations. The derivation of the prewarping expressions is explained with reference to these mappings, and the effect they have on the apparent pole and zero locations of an SC filter realization

Continuous-time low-pass filters for integrated wideband radio receivers

This thesis concentrates on the design and implementation of analog baseband continuous-time low-pass filters for integrated wideband radio receivers. A total of five experimental analog baseband low-pass filter circuits were designed and implemented as a part of five single-chip radio receivers in this work. After the motivation for the research work presented in this thesis has been introduced, an overview of analog baseband filters in radio receivers is given first. In addition, a review of the three receiver architectures and the three wireless applications that are adopted in the experimental work of this thesis is presented. The relationship between the integrator non-idealities and integrator Q-factor, as well as the effect of the integrator Q-factor on the filter frequency response, are thoroughly studied on the basis of a literature review. The theoretical study that is provided is essential for the gm-C filter synthesis with non-ideal lossy integrators that is presented after the introduction of different techniques to realize integrator-based continuous-time low-pass filters. The filter design approach proposed for gm-C filters is original work and one of the main points in this thesis, in addition to the experimental IC implementations. Two evolution versions of fourth-order 10-MHz opamp-RC low-pass filters designed and implemented for two multicarrier WCDMA base-station receivers in a 0.25-µm SiGe BiCMOS technology are presented, along with the experimental results of both the low-pass filters and the corresponding radio receivers. The circuit techniques that were used in the three gm-C filter implementations of this work are described and a common-mode induced even-order distortion in a pseudo-differential filter is analyzed. Two evolution versions of fifth-order 240-MHz gm-C low-pass filters that were designed and implemented for two single-chip WiMedia UWB direct-conversion receivers in a standard 0.13-µm and 65-nm CMOS technology, respectively, are presented, along with the experimental results of both the low-pass filters and the second receiver version. The second UWB filter design was also embedded with an ADC into the baseband of a 60-GHz 65-nm CMOS radio receiver. In addition, a third-order 1-GHz gm-C low-pass filter was designed, rather as a test structure, for the same receiver. The experimental results of the receiver and the third gm-C filter implementation are presented

Switched-current filtering systems: design, synthesis and software development

Allpass filters are commonly employed in many applications to perform group delay equalisation in the passband. They are non-minimum phase by definition and are characterised by poles and zeros in mirror-image symmetry. SI allpass filters of both cascade biquad and bilinear-LDI ladder types have been in existence. These were implemented using Euler based integrators. Cascade biquads are known to have highly sensitive amplitude responses and Euler integrators suffer from excess phase. The equalisers that are proposed here are based on bilinear integrators instead of Euler ones. Derivation of these equalisers can proceed from either the s-domain, or directly from the z-domain, where a prototype is synthesised using the respective continued-fractions expansions, and simulated using standard matrix methods. The amplitude response of the bilinear allpass filter is shown to be completely insensitive to deviations in the reactive ladder section. Simulations of sensitivities and non-ideal responses reveal the advantages and disadvantages of the various structures. Existing DI multirate filters have to date been implemented as direct-form FIR and IIR polyphase structures, or as simple cascade biquad or ladder structures with non-optimum settling times. FIR structures require a large number of impulse coefficients to realise highly selective responses. Even in the case of linear phase response with symmetric impulse coefficients, when the number of coefficients can be halved, significant overheads can be incurred by additional multiplexing circuitry. Direct-form IIR structures are simple but are known to be sensitive to coefficient deviations and structures with non-optimum settling times operate entirely at the higher clock frequency. The novel SI decimators and interpolators proposed are based on low sensitivity ladder structures coupled with FIR polyphase networks. They operate entirely at the lower clock frequency which maximises the time available for the memory cells to settle. Two different coupling architectures with different advantages and disadvantages are studied

Ultra-Low-Power Sensors and Receivers for IoT Applications

The combination of ultra-low power analog front-ends and CMOS-compatible transducers enable new applications, such as environmental monitors, household appliances, health trackers, etc. that are seamlessly integrated into our daily lives. Furthermore, wireless connectivity allows many of these sensors to operate both independently and collectively. These techniques collectively fulfil the recent surge of internet-of-things (IoT) applications that have the potential to fundamentally change daily life for millions of people.In this dissertation, the circuit and system design of wireless receivers and sensors is presented that explores the challenges of implementing long lifespan, high accuracy, and large coverage range IoT sensor networks. The first is a wake-up receiver (WuRX), which continuously monitors the RF environment to wake up a higher-power radio upon detection of a predetermined RF signature. This work both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator.Although pushing the prior WuRX performance boundary by orders of magnitude, the first work shows moderate sensitivity, inferior temperature robustness, and large area with external lumped components. Thus, the second work shows a miniaturized WuRX that is temperature-compensated, yet still consumes only nano-watt power and millimeter area while operating at 9 GHz. To further reduce the area, a global common-mode feedback is utilized across the envelope detector and baseband amplifier that eliminates the need for off-chip ac-coupling components. Multiple temperature-compensation techniques are proposed to maintain constant bandwidth of the signal path and constant clock frequency. Both WuRXs operate at 0.4 V supply, consume near-zero power and achieve ~-70 dBm sensitivity.Lastly, the first reported CMOS 2-in-1 relative humidity and temperature sensor is presented. A unified analog front-end interfaces on-chip transducers and converts the inputs into a frequency vis a high-linearity frequency-locked loop. An incomplete-settling switched-capacitor-based Wheatstone bridge is proposed to sense the inputs in a power-efficient fashion

Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications

Approximately 75% of the health care yearly budget of public health systems around the world is spent on the treatment of patients with chronic diseases. This, along with advances on the medical and technological fields has given rise to the use of preventive medicine, resulting on a high demand of wireless medical systems (WMS) for patient monitoring and drug safety research. In this dissertation, the main design challenges and solutions for designing a WMS are addressed from system-level, using off-the-shell components, to circuit implementation. Two low-power oriented WMS aiming to monitor blood pressure of small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram) of patients with chronic diseases (wearable) are presented. A power consumption vs. lifetime analysis to estimate the monitoring unit lifetime for each application is included. For the invasive/non-invasive WMS, in-vitro test benches are used to verify their functionality showing successful communication up to 2.1 m/35 m with the monitoring unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/ 88-hour lifetime in periodic/continuous operation. This results in an improvement of more than 50% compared with the lifetime commercial products. Additionally, this dissertation proposes transistor-level implementations of an ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier (VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/ electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2). The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications

Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non- Linear (ELIN) systems. They can handle large-signals in a low power environment under half the capacitor area required by the more popular ELIN Log-domain filters. Their inherent class-AB nature stems from the odd property of the sinh function at the heart of their companding operation. Despite this early realisation, the Sinh filtering paradigm has not attracted the interest it deserves to date probably due to its mathematical and circuit-level complexity. This Thesis presents an overview of the CMOS weak inversion Sinh filtering paradigm and explains how biomedical systems of low- to audio-frequency range could benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of high order Sinh continuous–time filters and more importantly to confirm their micro-power consumption and 100+ dB of DR through measured results presented for the first time. Novel high order Sinh topologies are designed by means of a systematic mathematical framework introduced. They employ a recently proposed CMOS Sinh integrator comprising only p-type devices in its translinear loops. The performance of the high order topologies is evaluated both solely and in comparison with their Log domain counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a corresponding and also novel Log domain class-AB topology, confirming that Sinh filters constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense of higher complexity and power consumption. The theoretical findings are validated by means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a 0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of ~60dB and 74μW power consumption from 2V power supply

Analogue filter networks: developments in theory, design and analyses

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