14 research outputs found

    Tri-band CMOS Circuit Dedicated for Ambient RF Energy Harvesting

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    RÉSUMÉ L'utilisation de systèmes sans fil connait une croissance rapide dans divers domaines tels que les réseaux de téléphonie cellulaire, Wi-Fi, Wi-Max, la radiodiffusion et les communications par satellite. Cette croissance mènera à une quantité considérable d'énergie électromagnétique générée dans l'air ambiant, mais toujours en dessous des limites de sécurité internationales. Ainsi, la recherche au niveau des systèmes de récupération d'énergie RF pour alimenter des appareils électroniques miniaturisés à faible consommation de puissance devient attrayante et prometteuse. Le bloc principal dans un système de récupération d'énergie RF est le redresseur qui détermine l'efficacité et la sensibilité de l'ensemble du système. Étant donné que la puissance RF ambiante est très faible, la quantité d'énergie captée par l'antenne l’est également. En outre, il y a des pertes au niveau du réseau d'adaptation d’impédance qui réduisent encore plus la puissance transmise au bloc redresseur. Par conséquent, la puissance disponible est trop faible pour faire fonctionner des redresseurs classiques. Dans ce mémoire, nous proposons trois redresseurs à trois-étages et à grilles totalement croisées-couplées en utilisant des transistors à faible tension de seuil afin d’opérer à de faibles puissances d'entrée. Les trois redresseurs ont été conçus et intégrés au sein d’une même puce fabriquée en utilisant une technologie CMOS 130nm d’IBM. Ils ont été optimisés à des fréquences de 880MHz, 1960MHz et 2.45GHz respectivement. Les résultats expérimentaux démontrent qu’ils atteignent une efficacité de conversion de puissance maximale de 62%, 62% et 56.2% respectivement. Les mesures montrent également une grande amélioration de l'efficacité à de faibles niveaux de puissance d'entrée. Afin de récupérer l'énergie ambiante de trois principales sources RF au Canada – GSM-850, GSM-1900 et Wi-Fi, un système de redresseur utilisé pour la combinaison de la puissance de ces trois canaux est simulé et analysé. Le système utilise une topologie consistant simplement à connecter les sorties des redresseurs ensemble pour charger le condensateur de charge. En dépit de la grande amélioration de l'efficacité et de la sensibilité dans la plage de 0-5μW, une baisse d'efficacité indésirable se produit aux puissances plus élevées. Ainsi, un nouveau bloc de gestion de l'alimentation est proposé. De plus, une antenne tri-bande est conçue et simulée pour diminuer le volume de l'ensemble du système de récupération d'énergie RF. En particulier, les pertes par réflexion obtenues sont de -25.43dB, -13.92dB et -12.73dB aux fréquences citées plus haut respectivement.---------- ABSTRACT Nowadays, the use of wireless systems has grown rapidly in various domains such as cellular phone networks, Wi-Fi, Wi-Max, radio broadcasting and satellite communications. The growing use of these wireless systems leads to considerable amount of electromagnetic energy generated in ambient air (of course, still below international safety limits). Thus the research in ambient RF energy harvesting system dedicated for powering up low-power-consumption miniaturized electronic devices becomes attractive and promising. The main block in a RF harvesting system is the rectifier which determines the efficiency and sensitivity of the whole system. Since ambient RF power is very low, the amount of power captured by the antenna is extremely low. Besides, there is loss on matching networks, thus the available power given to the rectifier block is too low for traditional rectifiers to operate. Therefore, in this master thesis, three three-stage fully gate cross-coupled rectifiers using low-thresholdvoltage transistors are proposed to overcome the dead zone in low input power range. The three rectifiers optimized at 880MHz, 1960MHz and 2.45GHz frequencies respectively are designed on one chip layout. Their experimental results are retrieved from this custom fabricated integrated circuit using IBM 130nm CMOS technology. They achieve peak efficiencies of 62%, 62% and 56.2% respectively and show great improvements on power conversion efficiency at low input power level. In order to harvest ambient RF energy from the three main RF contributors in Canada – GSM-850, GSM-1900 and Wi-Fi 2.4GHz, a rectifier system used for power combination from these three channels is simulated and analyzed. The system employs a simple topology by connecting the outputs together to charge the load capacitor. In spite of its high improvements on efficiency and sensitivity in 0-5μW range, an undesirable efficiency drop happens at higher input power levels. Thus an idea of power management block is proposed. In addition, a tri-band antenna is designed and simulated so as to decrease the volume of the overall RF energy harvesting system. It achieves return loss of -25.43dB, -13.92dB and - 12.73dB at each desired band respectively

    A 30mV input battery-less power management system

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    This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booster

    A 30mV Input Battery-Less Power Management System

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    This paper presents a fully-integrated on chip battery-less power management system through energy harvesting circuit developed in a 130nm CMOS process. A 30mV input voltage from a TEG is able to be boosted by the proposed Complementary Metal-Oxide-Semiconductor (CMOS) voltage booster and a dynamic closed loop power management to a regulated 1.2V. Waste body heat is harvested through Thermoelectric energy harvesting to power up low power devices such as Wireless Body Area Network. A significant finding where 1 Degree Celsius thermal difference produces a minimum 30mV is able to be boosted to 1.2V. Discontinuous Conduction Mode (DCM) digital control oscillator is the key component for the gate control of the proposed voltage booster. Radio Frequency (RF) rectifier is utilized to act as a start-up mechanism for voltage booster and power up the low voltage closed loop power management circuit. The digitally control oscillator and comparator are able to operate at low voltage 600mV which are powered up by a RF rectifier, and thus to kick-start the voltage booste

    HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

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    In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

    Low power rf transceivers

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    This thesis details the analysis and design of ultra-low power radio transceivers operating at microwave frequencies. Hybrid prototypes and Monolithic Microwave Integrated Circuits (MMICs) which achieve power consumptions of less than 1 mW and theoretical operating ranges of over 10 m are described. The motivation behind the design of circuits exhibiting ultra low power consumption and, in the case of the MMICs, small size is the emerging technology of Wireless Sensor Networks (WSN). WSNs consist of spatially distributed ‘nodes’ or ‘specks’ each with their own renewable energy source, one or more sensors, limited memory, processing capability and radio or optical link. The idea is that specks within a ‘speckzone’ cooperate and share computational resources to perform complex tasks such as monitoring fire hazards, radiation levels or for motion tracking. The radio section must be ultra low power e.g. sub 1 mW in order not to drain the limited battery capacity. The radio must also be small in size e.g. less than 5 x 5 mm so that the overall speck size is small. Also, the radio must still be able to operate over a range of at least a metre so as to allow radio contact between, for example, rooms or relatively distant specks. The unsuitability of conventional homodyne topologies to WSNs is discussed and more efficient methods of modulation (On-Off Keying) and demodulation (non-coherent) are presented. Furthermore, it is shown how Super-Regenerative Receivers (SRR) can be used to achieve relatively large output voltages for small input powers. This is important because baseband Op-Amps connected at the RF receiver output generally cannot amplify small signals at the input without the output being saturated in noise (10mV is the smallest measured input for 741 Op-Amp). Instrumentation amplifiers are used in this work as they can amplify signals below 1mV. The thesis details the analysis and design of basic RF building blocks: amplifiers, oscillators, switches and detectors. It also details how the circuits can be put together to make transceivers as well as describing various strategies to lower power consumption. In addition, novel techniques in both circuit and system design are presented which allow the power consumption of the radio to be reduced by as much as 97% whilst still retaining adequate performance. These techniques are based on duty cycling the transmitter and receiver and are possible because of the discontinuous nature of the On-Off Keying signal. In order to ease the sensitivity requirements of the baseband receive amplifier a design methodology for large output voltage receivers is presented. The designed receiver is measured to give a 5 mV output for an input power of -90 dBm and yet consumes less than 0.7 mW. There is also an appendix on the non linear modelling of the Glasgow University 50nm InP meta-morphic High Electron Mobility Transistor (50nm mHEMT) and one on the non linear modelling of a commercial Step Recovery diode (SRD). Models for the 50 nm mHEMT and the SRD are useful in the analysis, simulation and design of oscillators and pulse generators respectively

    A Low-Power BFSK/OOK Transmitter for Wireless Sensors

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    In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

    Conception et réalisation d'un nouveau transpondeur DSRC à faible consommation

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    To increase the efficiency and safety of the road traffic, new concepts and technologies have been developed in Europe since 1992 for RTTT applications (Road Traffic & Transport Telematics). These applications use the Dedicated Short Range Communications (DSRC) devices at 5.8 GHz (ISM band). In view of the reliability and success of this technology, the use of such equipment is thus extended to the EFC (Electronic Fee Collection) or e-toll and also in many other application areas such as fleet management, public transport and parking management. Due to the broad applications, these equipments are subject to various standards CEN/TC 278, CEN ENV (EN) 12253, ETSI, etc.... The DSRC system consists in a transceiver (reader) and transponders (tags). Industrial approaches are oriented to semi-passive transponder technology, which uses the same signal sent by the reader to retransmit, performing a frequency shift and encoding data to be transmitted. This design avoids the use of the local oscillators to generate the RF wave, as in active transponders, and save electrical energy of batteries. This allows the development of relatively low cost and small size transponders. Despite advances in integrated low-power circuits technology, this concept still requires a lithium battery to operate the transponder for a period of 4-6 years. However, with the expansion of these facilities, it appears that over the years the amount of lithium to destroy has become a crucial problem for the environment. Nowadays designing a completely autonomous DSRC transponder is not feasible, since the amount of energy required is still high (8 mA/3.6 V active mode). Nevertheless, reducing the transponder electrical power consumption, as a solution to at least double the battery life, could be a good start point to improve environment protection.In this thesis we propose a new DSRC transponder with an original statechart that considerably reduces the power consumption. After validation of the new low-power consumption mode, we studied the possibility to recharge the battery of the transponder by means of Wireless Energy Harvesting. The DSRC Toll Collection RF link budget was carried out in order to estimate the amount of energy available when a car with a transponder passes through a toll system. However, RF link budget at 5.8 GHz presents a low power density, since the car does not stay enough on the DSRC antenna's field to proceed to energy harvesting. Therefore we explored another ISM frequency, the 2.45 GHz. Thus the Wireless Energy Harvesting chapter aims to further the state of the art through the design and optimization of a novel RF harvesting board design. We demonstrated that an optimum RF-DC load is required in order to achieve high RF-DC conversion efficiency. Several rectifiers and rectennas were prototyped in order to validate the numerical studies. Finally, the results obtained in this thesis are in the forefront of the State-of-the-Art of Wireless Energy Harvesting for very low available power density.Afin d'augmenter l'efficacité et la sécurité du trafic routier, de nouveaux concepts et technologies ont été développés depuis 1992 en Europe pour les applications RTTT (Road Traffic & Transport Telematics). Ces applications utilisent les équipements DSRC qui supportent les transmissions à courte distance à 5.8GHz. Vues la fiabilité et le succès de cette technologie, l'utilisation de ces équipements est ensuite étendue aux ETC (Electronic Toll Collection) ou Télépéage et aussi dans une multitude d'autres domaines d'application comme la gestion des flottes, le transport public et la gestion des parkings. Le système DSRC se compose d'un émetteur/récepteur (lecteur) et des transpondeurs (badges). En toute logique, l'approche industrielle oriente les développements vers la technologie de transpondeur semi passif qui, pour réémettre un signal utilise le signal transmis par l'émetteur–récepteur, effectue une modulation de phase d'une sous porteuse fréquentielle encodant ainsi les données à transmettre. Cette conception évite l'utilisation des oscillateurs locaux, comme dans les transpondeurs actifs, pour générer l'onde Radio Fréquence (RF). Ceci permet de produire des transpondeurs relativement à faible coût et de petite taille. Cependant ce concept nécessite quand même une batterie au Lithium pour assurer le fonctionnement du transpondeur pour une durée de 4 à 6 ans et ce malgré les progrès des technologies de circuits intégrés à faible consommation. Au fur et à mesure de l'expansion de ces équipements, il s'avère qu'avec les années la quantité des batteries au lithium à détruire deviendrait un problème crucial pour l'environnement. Aujourd'hui, la conception d'un transpondeur DSRC complètement autonome n'est pas faisable, car la quantité d'énergie nécessaire s'avère encore élevée (mode actif 8 mA/3.6 V). Néanmoins, la réduction de la consommation électrique du transpondeur, permet au moins doubler la durée de vie de la batterie et pourrait être un bon point de départ pour améliorer la protection de l'environnement.Dans cette thèse, nous proposons un nouveau transpondeur DSRC avec un diagramme d'état original qui réduit considérablement la consommation énergétique. Après validation d'un nouvel état de fonctionnement en mode très faible consommation d'énergie, nous avons étudié la possibilité de recharger la batterie du transpondeur à travers de la récupération d'énergie sans fil. Le bilan de liaison énergétique DSRC a été réalisé afin d'estimer la quantité d'énergie disponible quand une voiture avec un transpondeur passe à sous un système de péage. Toutefois, le bilan énergétique à 5.8 GHz présente une faible densité d'énergie RF, puisque la voiture ne reste pas assez sur le lobe de l'antenne DSRC afin de procéder à la récupération d'énergie. Par conséquent, nous avons alors exploré une autre fréquence ISM, le 2.45 GHz dans laquelle la présence d'émetteurs est bien plus grande. Dans le chapitre de récupération d'énergie sans fil nous présentons la conception et l'optimisation d'un nouveau récupérateur d'énergie RF. Après avoir démontré qu'une charge RF-DC optimale est nécessaire afin d'atteindre une haute efficacité de conversion RF-DC. Plusieurs redresseurs et rectennas ont été conçus pour valider les études numériques. Parmi, les résultats présentés dans cette thèse les rendement de conversion obtenus sont à l'état de l'art de la récupération d'énergie sans fil pour une très faible densité de puissance disponible

    Stratégie d'alimentation pour les SoCs RF très faible consommation

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    Les réseaux de capteurs sans fil nécessitent des fonctions de calcul et de transmissionradio associées à chaque capteur. Les SoCs RF intégrant ces fonctions doivent avoir uneautonomie la plus grande possible et donc une très faible consommation. Aujourd'hui, leursperformances énergétiques pourraient être fortement améliorées par des systèmes d'alimentationinnovants. En effet, les circuits d'alimentation remplissent leur fonction classique de conversiond'énergie mais aussi des fonctions d'isolation des blocs RF et digitaux. Leurs performancess'évaluent donc en termes d'efficacité énergétique et de réponse transitoire mais aussi d'isolationentre blocs et de réjection de bruit.Ce travail de thèse concerne l'intégration du système de gestion et de distribution del énergie aux différents blocs RF d un émetteur/récepteur en élaborant une méthodologie topdown pour déterminer la sensibilité de chaque bloc à son alimentation et en construisant unearchitecture innovante et dynamique de gestion/distribution de l'énergie sur le SoC. Cetteméthodologie repose sur la disponibilité de régulateurs de tension présentant des performancesadaptées. Un deuxième volet du travail de thèse a donc été de réaliser un régulateur linéaire detype LDO à forte réjection sur une bande passante relativement large et bien adapté àl'alimentation de blocs RF très sensibles aux bruits de l'alimentation.Wireless sensor networks require calculation functions and radiofrequencytransmission modules within each sensor. RF SoCs integrating these functions must have thebiggest battery life and so a very small consumption. Today, innovative power managementsystems could highly enhance the energy performances of this type of RF SoC. Indeed, thesepower systems perform energy conversion and also the isolation functions of RF and digitalblocks. Their features are thus estimated in terms of energy efficiency, transient response and alsoisolation between blocks and noise rejection.This thesis work concerns the integration of the power management systems and itsdistribution channels into different ultra-low-power SoCs. This was achieved mainly thanks to thedevelopment of a new top-down approach. This new methodology consists of determining thesensibility of every block to its power supply and of designing an innovative and dynamicarchitecture of power management circuits on the SoC. This study ends up in the implementationof a very efficient low dropout (LDO) regulator for noise-sensitive low-current RF blocks inmixed SoC applications. The fabricated prototype achieves a high power supply rejection for awide range of frequencies.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF
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