Efficient RF energy scavenging and ultra-low power management for powering wireless sensor nodes

As the demand for real-time information in engineering and health care systems keeps increasing, the need for wireless sensor nodes is also continuously increasing. As a result, the cost and effort involved in installing and maintaining batteries to power the numerous sensor nodes is growing exponentially. Providing a cost effective and maintenance free alternate energy source is the motivation behind the development of energy scavenging solutions for self-powered sensor networks. In this research, an energy scavenging system that extracts energy from ambient radio-frequency waves transmitted in the 2.4GHz ISM band is designed. The harvested energy is efficiently managed with an ultra low-power switched capacitor buck-boost DC-DC converter to wirelessly power the nodes in a wireless sensor network. Analysis and optimization of the number of rectifier stages required to achieve efficient power conversion is carried out. To improve far field conversion efficiency and extend the scavenger sensitivity, the threshold voltage of the diodes in the rectifiers are reduced to about 50mV by using the floating-gate programming technique.The active power consumption of the switched-capacitor DC-DC converter is around 1.2μW. A micro-power analog to digital converter for variable gain selection and a sub-threshold linear voltage regulator for providing the start-up, are designed. The integrated system provides a fully autonomous micro-energy scavenging solution for the sensor nodes. The simulated results suggest that the scavenger achieves a 10% higher con- version efficiency than the most recently reported work. The operational distance of this improved energy scavenging solution is 6 meters (in free space) from an intentional RF transmitter operating under FCC specifications at 2.4GHz. The targeted application of this research is to provide an alternate energy solution for low power devices, including wireless sensor nodes and bio-medical applications

A Smart IoT Node using a Hybrid Edge-Computing Strategy for Environmental Multiparameter Sensing

The Internet of Things (IoT) has been growing at an immense pace over the last few years and there are no predictions of slowing down anytime soon, but most importantly, not only has it been growing in size but it has also been growing in capabilities, performance and diversity. Diversity is incredibly important but also fracturing, in this context. As IoT sensor nodes get more performant and diverse, their adaptability and reconfigurability ends up being lost in the search for ultimate performance. As a way to unify these individual single purpose sensor nodes, a need and an opportunity present themselves to develop a singular multi-parameter, multi-sensor IoT node, that can make use of the latest reconfigurable technology to adapt itself to the requirements of each type of sensor, while maintaining the very high performance and precision of dedicated sensor nodes. This dissertation work will thus focus on developing an architecture and building a prototype circuit board for a multi-sensor, reconfigurable IoT node based on a state-ofthe- art System-on-Chip (SoC) with extremely high resolution measurement capabilities, which can interface with virtually any type of existing sensor. This architecture and prototype are intended to serve as a stepping stone in the path to develop a capable IoT node which can interface with a wider range of sensor and have a higher precision than what is currently availableA Internet of Things (IoT) tem vindo a crescer a passos largos ao longo dos últimos anos, e não apresenta quaisquer sinais de abrandar o seu crescimento num futuro próximo. No entanto, não só tem vindo a crescer em tamanho, mas também nas suas capacidades, performance e diversidade. Enquanto que a diversidade é extremamente importante, neste contexto, é também fraturante. À medida que os nós IoT melhoram em performance e diversidade, a sua adaptabilidade e reconfigurabiliade acaba por ficar em segundo plano na procura do pico de performance. Com o objetivo de unificar estes nós de sensores com propósitos singulares, apresentase uma oportunidade e uma necessidade de desenvolver um único nó IoT capaz de fazer interface com uma multiplicidade de sensores distintos, usando tecnologia de ponta reconfigurável para se adaptar às necessidades de cada tipo de sensor, mantendo ainda assim a alta performance e precisão de nós de sensor dedicados. A presente dissertação irá então focar-se no desenvolvimento de uma arquitetura de sistema e criação de um protótipo em placa de circuito impresso referente a um nó IoT multisensor reconfigurável, baseado num SoC de última geração com capacidades de medição extremamente elevadas, que consiga fazer interface com qualquer tipo de sensor existente. Esta arquitetura de sistema e protótipo são desenvolvidos com a intenção de servirem como ponto de partida para o desenvolvimento de um nó IoT de interface com sensores, que tenha a capacidade de medir qualquer tipo de sensor com uma precisão superior àquilo que está atualmente disponível

Design of high-linearity PVT-robust dynamic amplifier

Modern electronic device market demands high power-efficiency, high-speed, and high-resolution analog-to-digital converters (ADC). Amplifiers be-come increasingly significant in the high-performance ADC design. Dynamic amplifier stands out for its low power consumption feature. However, the process-voltage-temperature (PVT) variation and limited linearity prevent it from wide usage. This thesis presents a high-linearity and PVT-robust dynamic amplifier. It implements the capacitively degenerated linearization (CDL) method to achieve high linearity. Furthermore, it combines a PVT-sensing amplifier and a voltage-to-time (V2T) converter as the control timer. Once the foreground calibration is done, the proposed dynamic amplifier will track the PVT variation and provide high-linearity and stable gain. Compared to the conventional CDL dynamic amplifier and the PVT-stabilized dynamic amplifier, this design suffers from less gain variation over PVT fluctuation while exhibiting high linearity. Therefore, it suits the application of the pipeline ADC and other types of ADC. A design prototype in schematic level is implemented in 40nm TSMC CMOS technology. The simulation results indicate that the circuit provides less than −80dB total-harmonics-distortion (THD), ranging from−15°C to 100°C with 140mV peak-to-peak differential sinusoidal input. When the supply voltage varies from 1.15V to 1.25V, the gain variation of this design is within ±2.5% and the THD is less than −75dB.Electrical and Computer Engineerin

Cmos Based Lensless Imaging Systems And Support Circuits

While much progress has been made in various fields of study in past few decades, leading to better understanding of science as well as better quality of life, the role of optical sensing has grown among electrical, chemical, optical, and other physical signal modalities. As an example, fluorescent microscopy has become one of the most important methods in the modern biology. However, broader implementation of optical sensing has been limited due to the expensive and bulky optical and mechanical components of conventional optical sensor systems. To address such bottleneck, this dissertation presents several cost-effective, compact approaches of optical sensor arrays based on solid state devices that can replace the conventional components. As an example, in chapter 2 we demonstrate a chip-scale (<1 mm2 ) sensor, the Planar Fourier Capture Array (PFCA), capable of imaging the far-field without any off-chip optics. The PFCA consists of an array of angle-sensitive pixels manufactured in a standard semiconductor process, each of which reports one component of a spatial two-dimensional (2D) Fourier transform of the local light field. Thus, the sensor directly captures 2D Fourier transforms of scenes. The effective resolution of our prototype is approximately 400 pixels. My work on this project [15] includes a circuit design and layout and the overall testing of the imaging system. In chapter 3 we present a fully integrated, Single Photon Avalanche Detector (SPAD) using only standard low- voltage (1.8V) CMOS devices in a 0.18m process. The system requires one highvoltage AC signal which alternately reverse biases the SPADs into avalanche breakdown and then resets with a forward bias. The proposed self-quenching circuit intrinsically suppresses after-pulse effects, improving signal to noise ratio while still permitting fine time resolution. The required high-voltage AC signal can be generated by resonant structures and can be shared across arrays of SPADs [24]. An ideal light sensor to provide the precise incident intensity, location, and angle of incoming photons is shown in chapter 4. Single photon avalanche diodes (SPADs) provide such desired high (single photon) sensitivity with precise time information, and can be implemented at a pixel scale to form an array to extract spatial information. Furthermore, recent work has demonstrated photodiode-based structures (combined with micro-lenses and diffraction gratings) that are capable of encoding both spatial and angular information of the incident light. In this chapter, we describe the implementation of such grating structure on SPAD to realize a pixel-scale angle-sensitive single photon avalanche diode (A-SPAD) using a standard CMOS process. While the underlying SPAD structure provides the high sensitivity, the diffraction gratings consisting of two sets of metal layers offers the angle-sensitivity. Such unique combination of the SPAD and the diffraction gratings expand the sensing dimensions to pave a path towards a lens-less 3-D imaging and a light-field timeof-flight imaging. In chapter 5, we present a 72 x 60, angle-sensitive single photon avalanche diode (A-SPAD) array for lens-less 3-D fluorescent life time imaging. A-SPAD pixels are comprised of (1) a SPAD to resolve precise timing information, to reject high-powered UV stimulus, and to map the lifetimes of different fluorescent sources and (2) integrated diffraction gratings on top of the SPAD to extract incident angles of incoming light, enabling 3-D localization at a micrometer scale. The chip presented in this work also integrates pixel-level counters as well as shared timing circuitry, and is implemented in conventional 180nm CMOS technology without any post-processing. Contact-based read- out from a revolving MEMS accelerometers is problematic therefore contactless (optical) read-out is preferred. The optical readout requires an image sensor to resolve nanometer-scale shifts of the MEMS image. Traditional imagers record on a rectangular grid which is not well-suited for efficiently imaging rotating objects due to the significant processing overhead required to translate Cartesian coordinates to angular position. Therefore, in chapter 6 we demonstrate a high-speed ( 1kfps), circular, CMOS imaging array for contact-less, optical measurement of rotating inertial sensors. The imager is designed for real-time optical readout and calibration of a MEMS accelerometer revolving at greater than 1000rpm. The imager uses a uniform circular arrangement of pixels to enable rapid imaging of rotational objects. Furthermore, each photodiode itself is circular to maintain uniform response throughout the entire revolution. Combining a high frame rate and a uniform response to motion, the imager can achieve sub-pixel resolution (25nm) of the displacement of micro scale features. In order to avoid fixed pattern noise arising from non-uniform routing within the array we implemented a new global shutter technique that is insensitive to parasitic capacitance. To ease integration with various MEMS platforms, the system has SPI control, on-chip bias generation, sub-array imaging, and digital data read-out. My work on this project [20] includes a circuit design and lay- out and some testing including, a FPGA based controller design of the imaging system. In the previous chapters, compact and cost effective imaging sys- tems have been introduced. Those imaging systems show great potential for wireless implantable systems. A power rectifier for the implant provides a volt- age DC power with a small inductor, for small volume, from a small AC voltage input. In the last chapter we demonstrate an inductively powered, orthogonal current-reuse multi-channel amplifier for power-efficient neural recording. The power rectifier uses the input swing as a self-synchronous charge pump, making it a fully passive, full-wave ladder rectifier. The rectifier supplies 10.37[MICRO SIGN]W at 1.224V to the multi-channel amplifier, which includes bias generation. The prototype device is fabricated in a TSMC 65nm CMOS process, with an active area of 0.107mm2 . The maximum measured power conversion efficiency (PCE) is 16.58% with a 184mV input amplitude. My work on this project [25] in- cludes the rectifier design and overall testing to combine "orthogonal currentreuse neural amplifier" designed by Ben Johnson

Design of Power Management Integrated Circuits and High-Performance ADCs

A battery-powered system has widely expanded its applications to implantable medical devices (IMDs) and portable electronic devices. Since portable devices or IMDs operate in the energy-constrained environment, their low-power operations in combination with efficiently sourcing energy to them are key problems to extend device life. This research proposes novel circuit techniques for two essential functions of a power receiving unit (PRU) in the energy-constrained environment, which are power management and signal processing. The first part of this dissertation discusses power management integrated circuits for a PRU. From a power management perspective, the most critical two circuit blocks are a front-end rectifier and a battery charger. The front-end CMOS active rectifier converts transmitted AC power into DC power. High power conversion efficiency (PCE) is required to reduce power loss during the power transfer, and high voltage conversion ratio (VCR) is required for the rectifier to enable low-voltage operations. The proposed 13.56-MHz CMOS active rectifier presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration. It is implemented with 5-V devices of a 0.35 µm CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200Ω loading. The linear battery charger stores the converted DC power into a battery. Since even small power saving can be enough to run the low-power PRU, a battery charger with low IvQ is desirable. The presented battery charger is based on a single amplifier for regulation and the charging phase transition from the constant-current (CC) phase to the constant-voltage (CV) phase. The proposed unified amplifier is based on stacked differential pairs which share the bias current. Its current-steering property removes multiple amplifiers for regulation and the CC-CV transition, and achieves high unity-gain loop bandwidth for fast regulation. The charger with the maximum charging current of 25 mA is implemented in 0.35 µm CMOS. A peak charger efficiency of 94% and average charger efficiency of 88% are achieved with an 80-mAh Li-ion polymer battery. The second part of this dissertation focuses on analog-to-digital converters (ADCs). From a signal processing perspective, an ADC is one of the most important circuit blocks in the PRU. Hence, an energy-efficient ADC is essential in the energy-constrained environment. A pipelined successive approximation register (SAR) ADC has good energy efficiency in a design space of moderate-to-high speeds and resolutions. Process-Voltage-Temperature variations of a dynamic amplifier in the pipelined-SAR ADC is a key design issue. This research presents two dynamic amplifier architectures for temperature compensation. One is based on a voltage-to-time converter (VTC) and a time-to-voltage converter (TVC), and the other is based on a temperature-dependent common-mode detector. The former amplifier is adopted in a 13-bit 10-50 MS/s subranging pipelined-SAR ADC fabricated in 0.13-µm CMOS. The ADC can operate under the power supply voltage of 0.8-1.2 V. Figure-of-Merits (FoMs) of 4-11.3 fJ/conversion-step are achieved. The latter amplifier is also implemented in 0.13-µm CMOS, consuming 0.11 mW at 50 MS/s. Its measured gain variation is 2.1% across the temperature range of -20°C to 85 °C

CMOS Transducers and Programmable Interface Circuits for Resource-Efficient Sensing Applications

Modern sensors are complex systems comprising multiple sub-systems such as transducers, analog and mixed-signal interface circuits, digital processing circuits, and packaging. Over the last few decades, innovations in these sub-systems combined with their increased integration in complementary metal-oxide semiconductor (CMOS) processes have led to the rapid growth in sensors for the Internet-of-Things (IoT), wearable devices, and fundamental scientific instrumentation. This thesis introduces novel ideas for various parts of a sensor signal chain. First, CMOS-based transducers (i.e. sensing elements) are introduced. Single-photon avalanche diodes (SPADs) fabricated in 0.18µm and 0.13µm standard CMOS processes are demonstrated and characterized for various optical sensing techniques. A resistor fabricated using standard CMOS-BEOL layers in a 0.18µm process is used to demonstrate a compact, fully-integrated single-element flow sensor occupying less than 0.065mm2. Second, front-end interface circuits for single-photon optical detectors are introduced. A fully-integrated SPAD-based ambient light sensor using mostly digital circuits and fabricated in a 0.13µm CMOS process is highlighted. It consumes 125μW and achieves one of the lowest reported areas (0.046mm2) in the literature. A custom analog front-end (AFE) chip is fabricated in a 0.18µm CMOS process for interfacing with a commercial silicon photomultiplier (SiPM) for gamma spectroscopy. It incorporates tunability of dynamic range and integration time, thus making it suitable for different detectors (i.e. SiPM and scintillator crystal combinations). Third, non-linear analog-to-digital converters (NL-ADCs) are explored as a viable alternative to linear ADCs for information-aware, non-uniform quantization and a widely reconfigurable piecewise-linear analog-to-digital converter (PWL-ADC) prototype chip (0.18µm CMOS) is used to validate this. With a 7-bit output word, it achieves 5.6-bit to 9.5-bit resolution in user-defined regions of the input full-scale range (FSR), while consuming 105µW at a sampling frequency of 42kHz. Measurements with recorded ECG waveforms are used to highlight the application-specific advantages of the PWL-ADC. Finally, some of the aforementioned ideas are used at the system level in a gamma spectrometer realized on a printed circuit board (PCB). The PCB design includes the AFE and PWL-ADC IC chips, a commercial SiPM and scintillator crystal, and a FPGA-based digital back-end (DBE). Several linear and non-linear isotope spectra with variable energy bin-widths (dE/bin) are recorded and analyzed to demonstrate the utility of the proposed concepts for peak enhancement and improved peak discrimination in radiation spectroscopy

A Bulk Driven Transimpedance CMOS Amplifier for SiPM Based Detection

The contribution of this work lies in the development of a bulk driven operationaltransconducctance amplifier which can be integrated with other analog circuits andphotodetectors in the same chip for compactness, miniaturization and reducing thepower. Silicon photomultipliers, also known as SiPMs, when coupled with scintillator materials are used in many imaging applications including nuclear detection. This thesis discuss the design of a bulk-driven transimpedance amplifier suitable for detectors where the front end is a SiPM. The amplifier was design and fabricated in a standard standard CMOS process and is suitable for integration with CMOS based SiPMs and commercially available SiPMs. Specifically, the amplifier was verified in simulations and experiment using circuit models for the SiPM. The bulk-driven amplifier’s performance, was compared to a commerciallyavailable amplifier with approximately the same open loop gain (70dB). Bothamplifiers were verified with two different light sources, a scintillator and a SiPM.The energy resolution using the bulk driven amplifier was 8.6% and was 14.2% forthe commercial amplifier indicating the suitability of the amplifier design for portable systems

Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays

Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through the skull has prevented ultrasound imaging of the brain. This research is a prime step toward implantable wireless microsystems that use ultrasound to image the brain by bypassing the skull. These microsystems offer autonomous scanning (beam steering and focusing) of the brain and transferring data out of the brain for further processing and image reconstruction. The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their associated integrated electronics in terms of electrical power transfer and acoustic reflection which would potentially lead to more efficient and high-performance systems. A fully wireless architecture for ultrasound imaging is demonstrated for the first time. An on-chip programmable transmit (TX) beamformer enables phased array focusing and steering of ultrasound waves in the transmit mode while its on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB) uplink transmitter minimizes the effect of path loss on the transmitted image data out of the brain. A single-chip application-specific integrated circuit (ASIC) is de- signed to realize the wireless architecture and interface with array elements, each of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser, a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building blocks. Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems. In addition, the effect of matching and electrical termination on CMUT array elements is explored leading to new interface structures to improve bandwidth and sensitivity of CMUT arrays in different operation regions. Comprehensive analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D

Heterogeneous Chip Multiprocessor: Data Representation, Mixed-Signal Processing Tiles, and System Design

With the emergence of big data, the need for more computationally intensive processors that can handle the increased processing demand has risen. Conventional computing paradigms based on the Von Neumann model that separates computational and memory structures have become outdated and less efficient for this increased demand. As the speed and memory density of processors have increased significantly over the years, these models of computing, which rely on a constant stream of data between the processor and memory, see less gains due to finite bandwidth and latency. Moreover, in the presence of extreme scaling, these conventional systems, implemented in submicron integrated circuits, have become even more susceptible to process variability, static leakage current, and more. In this work, alternative paradigms, predicated on distributive processing with robust data representation and mixed-signal processing tiles, are explored for constructing more efficient and scalable computing systems in application specific integrated circuits (ASICs). The focus of this dissertation work has been on heterogeneous chip multi-processor (CMP) design and optimization across different levels of abstraction. On the level of data representation, a different modality of representation based on random pulse density modulation (RPDM) coding is explored for more efficient processing using stochastic computation. On the level of circuit description, mixed-signal integrated circuits that exploit charge-based computing for energy efficient fixed point arithmetic are designed. Consequently, 8 different chips that test and showcase these circuits were fabricated in submicron CMOS processes. Finally, on the architectural level of description, a compact instruction-set processor and controller that facilitates distributive computing on System-On-Chips (SoCs) is designed. In addition to this, a robust bufferless network architecture is designed with a network simulator, and I/O cells are designed for SoCs. The culmination of this thesis work has led to the design and fabrication of a heterogeneous chip multi- processor prototype comprised of over 12,000 VVM cores, warp/dewarp processors, cache, and additional processors, which can be applied towards energy efficient large-scale data processing