Vedic-Based Squarers with High Performance

Squaring operation represents a vital operation in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, a novel design for a 6-bit squarer basing on the Vedic multiplier (VM) is offered in this work. The squarer design utilizes dedicated 3-bit squarer modules, a (3*3) VM, and an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with the amended design of XOR gate to perform fast partial-products addition. The 6-bit squarer circuit can readily be expanded for larger sizes such as 12-bit and 24-bit numbers which are useful for squaring the mantissa part of  32-bit floating-point numbers. The paper also offers three architectures for 24- bit squarer using pipelining concept used in various stages. All these squaring circuits are designed in VHDL and implemented by Xilinx ISE13.2 and FPGA. The synthesis results reveal that the offered 6-bit, 12- bit, and 24- bit squarer circuits introduce eminent outcomes in terms of delay and area when utilizing IBK-CSLA with amended XOR gate. Also, it is found that the three architectures of 24- bit squarer present dissimilar delay and area, and the architecture design based on 3-bit squarer modules with  (3*3) VM introduces the lowest area and delay

FPGA Implementation & Performance Comparision of Various High Speed unsigned Binary Multipliers using VHDL

Today, most of the DSP computations involve the use of multiply accumulate operations and therefore the design of fast and efficient multipliers is imperative. The addition and multiplication of two binary numbers is the fundamental and most often used arithmetic operation in microprocessors, digital signal processors and data-processing application-specific integrated circuits. In this paper, we present the study of different types of multipliers by comparing the speed and area of each. In this work, VHDL coding and XILINX ISE Simulator is employed to implement multipliers like WTM, Dadda Multiplier, Vedic Multiplier, CSHM, Serial Multiplier and Multipliers using different compressors in Wallace tree architecture. The analysis of this work would be helpful to choose a better multiplier in order to fabricate an efficient system

A 2x2 Bit Multiplier Using Hybrid 13T Full Adder with Vedic Mathematics Method

Various arithmetic circuits such as multipliers require full adder (FA) as the main block for the circuit to operate. Speed and energy consumption become very vital in design consideration for a low power adder. In this paper, a 2x2 bit Vedic multiplier using hybrid full adder (HFA) with 13 transistors (13T) had been designed successfully. The design was simulated using Synopsys Custom Tools in General Purpose Design Kit (GPDK) 90 nm CMOS technology process. In this design, four AND gates and two hybrid FA (HFAs) are cascaded together and each HFA is constructed from three modules. The cascaded module is arranged in the Vedic mathematics algorithm. This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which reduced the number of partial products compared to the conventional multiplication algorithm. With the combination of hybrid full adder and Vedic mathematics, a new combination of multiplier method with low power and low delay is produced. Performance parameters such as power consumption and delay were compared to some of the existing designs. With a 1V voltage supply, the average power consumption of the proposed multiplier was found to be 22.96 µW and a delay of 161 ps

Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA

In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques. Further, the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator

Power-Effective Vedic-Hierarchical Multiplier

The motivation of this project is to design a power effective multiplier without having much drawback in term of time constraint and area utilization. This is due to the overall power dissipation which increases in direct proportion to the increase in power density. The area and time constraint are considered as pertinent design parameters with the increase in market demand for high performance and complex portable systems. The current hierarchical multiplier designs suffer on long critical path and large area utilization. These parameters caused the hierarchical multiplier design to be less effective in term of power saving. The objective of this research is to reduce overall power dissipation and ensure that the multiplier achieve timing requirement. This paper proposes the design 1 by using two 4-bit Binary-to-Excess-One Converter (BEC) instead of an 8-bit BEC. The BEC reduce the critical path and cause low power dissipation. Design 2 which is implementation of Carry Select Adder (CSlA) with tristate buffer is to reduce logic elements. The power dissipation is reduced because of the decrease in the number of logic elements which leads to the lower number of logic gates. Both advantages of design 1 and design 2 are combined to become design 3. Design 3 is the lowest power dissipation design because it consists of the lowest number of logic elements and the shortest critical path. The timing requirement for all designs are met as shown by the positive slack time of 9.034 ns, 8.686 ns and 9.404 ns respectively. The power dissipation of the combinational multipliers designs have been improved to 60.96%, 60.89% and 61.02% respectively

An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform

In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device

A 4x4 Bit Vedic Multiplier with Different Voltage Supply in 90 nm CMOS Technology

In recent years, due to the rapid growth of high performance digital systems, speed and power consumption become very vital in multiplier design. In this paper, a 4x4 bit Vedic multiplier has been designed using the combination of Urdhva Triyakbyam Sutra and 13T hybrid full adder (HFA). This algorithm satisfied the requirement of a fast multiplication operation because of the vertical and crosswise architecture from the Urdhva Triyakbyam Sutra which minimize the number of partial products compared to the conventional multiplication algorithm. The multiplier is simulated using Synopsys Custom Tools with General Process Design Kit (GPDK) of 90 nm CMOS technology using several voltage supplies to find the most optimum value for the voltage supply to be used. The result shows that with the usage of 1 V voltage supply, the new design of multiplier using a combination of HFA and Vedic mathematics is able to produce the lowest power consumption and least delay time. The 4x4 bit Vedic multiplier is able to yield a full output voltage swing with a power consumption of only 0.2015 mW, delay of 376 ps and compact area of 3100 µm2

Wallace Tree Multiplier Designs: A Performance Comparison Review

Multiplication process is often used in digital signal processing systems, microprocessors designs, communication systems, and other application specific integrated circuits. Multipliers are complex units and play an important role in deciding the overall area, speed and power consumption of digital designs. This paper presents a comparison review of various Wallace tree multiplier designs in terms of parameters like latency, complexity and power consumption. Keywords: Booth Recoding Algorithm, Carry Look Ahead Adder, Carry Select Adder, Compressors, Ripple Carry Adder, Sklansky Adder, Wallace Tree Multipliers

Performance Boosting Components of Vedic DSP Processor

This paper deals with performance boosting of the DSP processor, by introducing the different algorithms in processor blocks ALU, MAC, Encoder/ decoder at. al. To in decrease the processing delay of Brent Kung adder is used, instead of other adder. Vedic sutras like Urdhava Tiryagbhyam and nikhilam sutras are used to increase the speed floating point multiplier, MAC and filters and other signal computations. The verilog HDL is used and the validated through extensive simulation. Synthesis results and attainment scrutiny of each systems components confirmed significant performance meliorism in the proffered DSP processor over the extant one