The Direct Summation of Totally Self-Checking Checkers

A new technique for reducing the complexity of designing Totally Self-Checking (TSC) checkers for m-out-of-n codes is presented. The method is based on the partitioning of the input variables into r classes, then partitioning the code groups generated into Z output partitions. Comparison with earlier results reveals improvements in design simplicity and logic and testing complexity. This thesis also presents a new method of TSC checker design where a j-level m1/n1 code and a k-level m2/n2 code TSC checker are directly summed to form a max [j,k]-level (m1 + m2) / (n1 + n2) TSC checker. A library of m/n code TSC checkers can then be used as building blocks for other m/n code TSC checkers

Formal Verification of Probabilistic SystemC Models with Statistical Model Checking

Transaction-level modeling with SystemC has been very successful in describing the behavior of embedded systems by providing high-level executable models, in which many of them have inherent probabilistic behaviors, e.g., random data and unreliable components. It thus is crucial to have both quantitative and qualitative analysis of the probabilities of system properties. Such analysis can be conducted by constructing a formal model of the system under verification and using Probabilistic Model Checking (PMC). However, this method is infeasible for large systems, due to the state space explosion. In this article, we demonstrate the successful use of Statistical Model Checking (SMC) to carry out such analysis directly from large SystemC models and allow designers to express a wide range of useful properties. The first contribution of this work is a framework to verify properties expressed in Bounded Linear Temporal Logic (BLTL) for SystemC models with both timed and probabilistic characteristics. Second, the framework allows users to expose a rich set of user-code primitives as atomic propositions in BLTL. Moreover, users can define their own fine-grained time resolution rather than the boundary of clock cycles in the SystemC simulation. The third contribution is an implementation of a statistical model checker. It contains an automatic monitor generation for producing execution traces of the model-under-verification (MUV), the mechanism for automatically instrumenting the MUV, and the interaction with statistical model checking algorithms.Comment: Journal of Software: Evolution and Process. Wiley, 2017. arXiv admin note: substantial text overlap with arXiv:1507.0818

Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults

[[abstract]]We present in this paper an approach to designing partially strongly code-disjoint (PSCD) CMOS circuits and checkers, considering transistor stuck-on faults in addition to gate-level stuck-at faults. Our design-for-testability (DFT) technique requires only a small number of extra transistors for monitoring abnormal static currents, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry not only can detect the faults in the functional circuit but also can detect or tolerate faults in itself, making it a good candidate for checker design. Switch and circuit level simulations were performed on a sample circuit, and a sample 4-out-of-8 code checker chip using the proposed technique has been designed, fabricated, and tested, showing the correctness of the method. Performance penalty is reduced by a novel BiCMOS checker circuit.[[fileno]]2030108010057[[department]]電機工程學

A Case Study of Self-Checking Circuits Reliability

In this paper, we analyze the reliability of self-checking circuits. A case study is presented in which a fault-tolerant system with duplicated self-checking modules is compared to the TMR version. It is shown that a duplicated self-checking system has a much higher reliability than that of the TMR counterpart. More importantly, the reliability of the selfchecking system does not drop as sharply as that of the TMR version. We also demonstrate the trade-offs between hardware complexity and error handling capability of self-checking circuits. Alternative self-checking designs where some hardware redundancies are removed with the lost of fault-secure and/or self-testing properties are also studied

Efficient design of CMOS TSC checkers

This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes

Parity Codes Used for On-Line Testing in FPGA

This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented.

On the self-testing (m,n)-code checker design

We propose an approach to a self-testing (m, n)code checker design, based on subdividing the set of all code words into special subsets called segments. The checker circuit is constructed by using one- and two-output configurable logic blocks (CLB). Previously, in each output of a CLB, a function representing exactly one segment was implemented. In the proposed approach, at each CLBs output, it is possible to implement functions that represent several segments and to provide the self-testing property. It allows reducing the number of CLBs and simplifying the circuit of the checker