Reversible Quantum-Dot Cellular Automata-Based Arithmetic Logic Unit

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell andelectrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lowerpower, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer’s central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCA Designer-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area

Implementation of Binary to Gray Code Converters in Quantum Dot Cellular Automata

Quantum dot cellular automaton (QCA) are dominant nanotechnology which has been used extensively in digital circuits and systems. It is a promising alternative to complementary metal–oxide–semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, QCA based 2-bit binary-to- gray; 3-bit binary-to-gray and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area and raises switching speed. The simulations are completed using QCADesigner and Microwindlite tool which is widely used for simulation and verification

Novel ultra-energy-efficient reversible designs of sequential logic quantum-dot cellular automata flip-flop circuits

The version of record of this article, first published in [The Journal of Supercomputing], is available online at Publisher’s website: http://dx.doi.org/10.1007/s11227-023-05134-1Quantum-dot cellular automata (QCA) is a technological approach to implement digital circuits with exceptionally high integration density, high switching frequency, and low energy dissipation. QCA circuits are a potential solution to the energy dissipation issues created by shrinking microprocessors with ultra-high integration densities. Current QCA circuit designs are irreversible, yet reversible circuits are known to increase energy efficiency. Thus, the development of reversible QCA circuits will further reduce energy dissipation. This paper presents novel reversible and irreversible sequential QCA set/reset (SR), data (D), Jack Kilby (JK), and toggle (T) flip-flop designs based on the majority gate that utilizes the universal, standard, and efficient (USE) clocking scheme, which allows the implementation of feedback paths and easy routing for sequential QCA-based circuits. The simulation results confirm that the proposed reversible QCA USE sequential flip-flop circuits exhibit energy dissipation less than the Landauer energy limit. Irreversible QCA USE flip-flop designs, although having higher energy dissipation, sometimes have floorplan areas and delay times less than those of reversible designs; therefore, they are also explored. The trade-offs between the energy dissipation versus the area cost and delay time for the reversible and irreversible QCA circuits are examined comprehensively

SYNTHESIS OF COMPOSITE LOGIC GATE IN QCA EMBEDDING UNDERLYING REGULAR CLOCKING

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design’s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation

Virtual Clocking for NanoMagnet Logic

Among emerging technologies nanomagnet logic (NML) has recently received particular attention. NML uses magnets as constitutive elements, and this leads to logic circuits where there is no need of an external power supply to maintain their logic state. As a consequence, a system with intrinsic memory and zero stand-by power consumption can be envisioned. Despite the interesting nature of NML, a fundamental open problem still calls for a solution that could really boost the NML technology: the clock system. It constrains the layout of circuits and leads to a potentially high dynamic power consumption if not carefully conceived. The first clock system developed was based on the generation of a magnetic field through an on-chip current. After that other types of NML, based on several different types of clock systems, were proposed to improve clocking. We present here our proposal for a new clock delivery method. We named this system “virtual clock.” It offers several important advantages over previous solutions. First, it notably simplifies the clock generation network, reducing the complexity of the fabrication process. It improves the efficiency of circuits layout, substantially reducing interconnections overhead and boosting the reliability of the majority voter. It enables the fabrication of in-plane NML circuits with two layers, while they were confined to one single layer up to now. Finally, it allows to globally reduce dynamic power consumption by considerably shrinking circuits area. Overall the “virtual clock” system that we propose represents an important step forward in the development of the NML technology

An Ultra-Energy-Efficient Reversible Quantum-Dot Cellular Automata 8:1 Multiplexer Circuit

Energy efficiency considerations in terms of reduced power dissipation are a significant issue in the design of digital circuits for very large-scale integration (VLSI) systems. Quantum-dot cellular automata (QCA) is an emerging ultralow power dissipation approach, distinct from traditional, complementary metal-oxide semiconductor (CMOS) technology, for building digital computing circuits. Developing fully reversible QCA circuits has the potential to significantly reduce energy dissipation. Multiplexers are fundamental elements in the construction of useful digital circuits. In this paper, a novel, multilayer, fully reversible QCA 8:1 multiplexer circuit with ultralow energy dissipation is introduced. The power dissipation of the proposed multiplexer is simulated using the QCADesigner-E version 2.2 tool, describing the microscopic physical mechanisms underlying the QCA operation. The results show that the proposed reversible QCA 8:1 multiplexer consumes 89% less energy than the most energy-efficient 8:1 multiplexer circuit previously presented in the literature

Nanoarchitecture of Quantum-Dot Cellular Automata (QCA) Using Small Area for Digital Circuits

Novel digital technologies always lead to high density and very low power consumption. One of these concepts—quantum-dot cellular automata (QCA), which is one of the new emerging nanotechnologies, is based on Coulomb repulsion. This chapter presents a novel design of 2-input Exclusive-NOR (XNOR)/Exclusive-OR (XOR) gates with 3-input Exclusive-NOR (XNOR) gates which are composed of 10 cells on 0.006 μm2 of area. A novel architecture of 3-input Exclusive-OR (XOR) gate is defined by 12 cells on 0.008 μm2 of area. The proposed design of 2-input XOR/XNOR gate structures provide less area and low complexity than the best reported design. The simulation results of proposed designs have been achieved using QCA Designer tool version 2.0.3

Flip Flops Design in Quantum Dot Cellular Automata Technology: Towards Digitization

Quantum-Dot Cellular Automata (QCA) is a transistor-less technology. In QCA, Columbic repulsion between electrons in the quantum dots makes data transfer possible. This paper presents the design of flip flops using a proposed Rotated-Normal Cells with Displacement (RND) inverter and a cell interaction method. The SR latch, SR Flip Flop (FF), D FF, and T FF are developed using QCA. The proposed D FF gives total and average energy dissipation of 1.31e-002eV and 1.19e-003eV respectively. It also gives a delay of 1 clock phase.  The Proposed T FF provides total and average energy dissipation of 2.40e-002eV and 2.18e-003eV respectively, depicting efficient D FF and T FF in energy dissipation. The proposed SR Flip flop design gives an efficient area. The FFs with the proposed RND inverter and cell interaction method can be the best choice for future Nano communication to construct Nano circuits with less energy dissipation and high speed

Cost-effective Programmable Logic Arrays Using Multilayer Structures of Decoders in QCA Framework

The emerging nanotechnology paradigm, Quantum Dot Cellular Automata (QCA) in particular, is gaining a wide recognition due to its high speed, nano feature size and considerably low power consumption. The QCA architecture not only provide potential alternative for Complementary Metal Oxide Semiconductor (CMOS) circuits but its multilayer topology facilitates an added benefit of cost efficacy and immunity towards random interference. Moreover, design of programmable logic devices in QCA is vital to promote the multi-utility and resiliency of the computing circuits. This paper presents the multilayer designs of 2×4 and 3×8 decoder circuits in QCA framework with 55.1% and 51.17% better cost efficiency respectively, over the earlier reported designs. The presented 3×8 decoder circuit is further utilized to implement Programmable Logic Array (PLA) to realize Boolean functions of adder and subtractor. The presented circuits are cost effective and showcase the significance of programmable devices in nano-computing