Asynchronous Early Output Dual-Bit Full Adders Based on Homogeneous and Heterogeneous Delay-Insensitive Data Encoding

This paper presents the designs of asynchronous early output dual-bit full adders without and with redundant logic (implicit) corresponding to homogeneous and heterogeneous delay-insensitive data encoding. For homogeneous delay-insensitive data encoding only dual-rail i.e. 1-of-2 code is used, and for heterogeneous delay-insensitive data encoding 1-of-2 and 1-of-4 codes are used. The 4-phase return-to-zero protocol is used for handshaking. To demonstrate the merits of the proposed dual-bit full adder designs, 32-bit ripple carry adders (RCAs) are constructed comprising dual-bit full adders. The proposed dual-bit full adders based 32-bit RCAs incorporating redundant logic feature reduced latency and area compared to their non-redundant counterparts with no accompanying power penalty. In comparison with the weakly indicating 32-bit RCA constructed using homogeneously encoded dual-bit full adders containing redundant logic, the early output 32-bit RCA comprising the proposed homogeneously encoded dual-bit full adders with redundant logic reports corresponding reductions in latency and area by 22.2% and 15.1% with no associated power penalty. On the other hand, the early output 32-bit RCA constructed using the proposed heterogeneously encoded dual-bit full adder which incorporates redundant logic reports respective decreases in latency and area than the weakly indicating 32-bit RCA that consists of heterogeneously encoded dual-bit full adders with redundant logic by 21.5% and 21.3% with nil power overhead. The simulation results obtained are based on a 32/28nm CMOS process technology

DESIGN AND PERFORMANCE ANALYSIS OF FULL ADDER USING 6-T XOR–XNOR CELL

In this paper, the design and simulation of a high-speed, low power 6-T XOR-XNOR circuit is carried out. Also, the design and simulation of 1-bit hybrid full adder (consisting of 16 transistors) using XOR-XNOR circuit, sum, and carry, is performed to improve the area and speed performance. Its performance is being compared with full adder designs with 20 and 18 transistors, respectively. The performance of the proposed circuits is measured by simulating them in Microwind tool using 180 and 90nm CMOS technology. The performance of the proposed circuit is measured in terms of power, delay, and PDP (Power Delay Product)

Latency Optimized Asynchronous Early Output Ripple Carry Adder based on Delay-Insensitive Dual-Rail Data Encoding

Asynchronous circuits employing delay-insensitive codes for data representation i.e. encoding and following a 4-phase return-to-zero protocol for handshaking are generally robust. Depending upon whether a single delay-insensitive code or multiple delay-insensitive code(s) are used for data encoding, the encoding scheme is called homogeneous or heterogeneous delay-insensitive data encoding. This article proposes a new latency optimized early output asynchronous ripple carry adder (RCA) that utilizes single-bit asynchronous full adders (SAFAs) and dual-bit asynchronous full adders (DAFAs) which incorporate redundant logic and are based on the delay-insensitive dual-rail code i.e. homogeneous data encoding, and follow a 4-phase return-to-zero handshaking. Amongst various RCA, carry lookahead adder (CLA), and carry select adder (CSLA) designs, which are based on homogeneous or heterogeneous delay-insensitive data encodings which correspond to the weak-indication or the early output timing model, the proposed early output asynchronous RCA that incorporates SAFAs and DAFAs with redundant logic is found to result in reduced latency for a dual-operand addition operation. In particular, for a 32-bit asynchronous RCA, utilizing 15 stages of DAFAs and 2 stages of SAFAs leads to reduced latency. The theoretical worst-case latencies of the different asynchronous adders were calculated by taking into account the typical gate delays of a 32/28nm CMOS digital cell library, and a comparison is made with their practical worst-case latencies estimated. The theoretical and practical worst-case latencies show a close correlation....Comment: arXiv admin note: text overlap with arXiv:1704.0761

Design and Analysis of Low Run-time Leakage in a 13 Transistors Full adder in 45nm Technology

In this paper a new full adder is proposed The number of Transistors used in the proposed full adder is 13 Average leakage is 62 of conventional 28 transistor CMOS full adder The leakage power reduction results in overall power reduction The proposed full adder is evaluated by virtuoso simulation software using 45 nm technology of cadence tool

Design of Hybrid Full Adder using 6T-XOR-Cell for High Speed Processor Designs Applications

Hybrid-logic implementation is highly suitable in the design of a full adder circuit to attain high-speed low-power consumption, which helps to design n any high speed ALUs that can be used in varies processors and applicable for high speed IoT- Application. XOR/XNOR-cell, Hybrid Full Adder (HFA) are the fundamental building block to perform any arithmetic operation. In this paper, different types of high-speed, low-power 6T-XOR/XNOR-cell designs are being proposed and simulated results are presented. The proposed HFA is simulated using a cadence virtuoso environment in a 45nm technology with supply voltage as 0.8V at 1GHz. The proposed HFA consumes a power of 1.555uw, and the delay is 36.692ns.  Layout designs are drawn for both 6T-XOR/XNOR-cell, and 1- bit HFA designs. XOR/XNOR-cells are designed based on the combination of normal CMOS-inverter and Pass Transistor Logic (PTL). Which is used in the design of high end device processors such as ALU that can be implemented for the IoT- design applications

Article 09415

ABSTRACT INTRODUCTION Today's there square measure a growing range of moveable applications requiring small-area low-power highoutturn electronic equipment. Therefore, circuits with low power utilization grow to be the foremost vital candidates for style of microprocessors and system mechanism. The battery technology doesn't advance at constant rate because the electronics technology and there's a imperfect amount of power on the market for the mobile systems. The goal of extending the battery lifetime of moveable natural philosophy is to cut back the energy consumed per mathematical process, however low power consumption doesn't primarily imply low energy. To execute associate mathematical process, a circuit will acquire through low power by continuance at terribly low frequency however it's going to take a really lasting to complete the operation. Adder is a standout amongest the most fundamental segments of a CPU ( Central processing unit), Arithmetic logic unit (ALU), and coasting point unit and location era like store or memory access unit. Then again, expanding interest for versatile supplies Such as phones, personal digital assistant (PDA), and Notebook PC, emerge the need of utilizing zone and Power proficient VLSI circuits. Conventional adder is one in all the chief essential components of a processor that decides its out turn, and for address era just if there should be an occurrence of reserve or operation the complete adder execution would have an impact on the system as a whole. a spread of full adders. Abuse static or dynamic logic gates are accounted within the literature. In this paper, have a tendency to propose a logical methodology to style 10-transistor full adders and 28t full adders. Our new adders even have the limit misfortune issue; in any case, the adders square measure supportive in bigger circuits like multipliers regardless of the edge misfortune disadvantage. a substitution full adder known as static energy recovery full adder utilizes exclusively 10 transistors that has the most modest sum scope of transistors and has reduces the power dissipation, for every Power decline is one in all the first issues in today's VLSI style techniques as a consequence of a few reasons one is that the long battery in operation life interest of movable gadgets and second is owing to expanding scope of transistors on one chip brings about high power dissipation. The power consumption for CMOS circuits is described by the following equation: P avg = P dynamic + P short circuit + P leak Pavg =fclkCLαiV 2 dd + fclkI short V dd + I leak V dd Clearly see that the power depends on different parameters as well as on supply voltage (Vdd). Lowering Vdd would significantly reduce the power consumption of the circuit. This basic concept would be utilized to improve the power performance of the adder in this paper

Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications

This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power-delay product (PDP) compared to its counterparts. According to the simulation results, the propagation delay of the proposed full adder is 22.8% less than the propagation delay of next fastest full adder, and the power-delay product of the proposed full adder is 22.7% less than the next best PDP. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits

Design of Low2power Full Adder Using Different Hybrid Logic Styles

Full adder is a basic and most important digital component. To improve the full adder architecture many improvements has been made. Here we present Hybrid CMOS full adder, ULP (Ultra low power) full adder and two new design full adders that is Hybrid logic style and GDI(gate diffusion input ) Structure. These two new full adders consists less number of transistors (i.e.12 transistors) compared to previously designed full adders. The motive of adder cell is to provide high speed, low power consumption and also to give high voltage swing. The Hybrid CMOS logic full adder and ULP full adder uses CPL logic, transmission gates and Static CMOS logic styles. New hybrid full adder uses semi XOR-XNOR gates and GDI-MUX full adder with a new design which eliminates the use XOR-XNOR gates and also uses GDI (gate diffusion input) cell with 12 transistors provides low power, high speed and also full voltage swing. Theses design are implemented in Cadence virtuoso software using 90nm technology GPDK tool kit and comparison of Power, Delay and Power delay product (PDP) is done