Ternary full adder using multi-threshold voltage graphene barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10-16 J, which is comparable with the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors