Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Integrated Microwave Photonic Processors using Waveguide Mesh Cores

Integrated microwave photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint and cost. Application Specific Photonic Integrated Circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long-development times and costly implementations. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable Microwave Photonic processor, where a common hardware implemented by the combination of microwave, photonic and electronic subsystems, realizes different functionalities through programming. Here, we propose the first-ever generic-purpose Microwave Photonic processor concept and architecture. This versatile processor requires a powerful end-to-end field-based analytical model to optimally configure all their subsystems as well as to evaluate their performance in terms of the radiofrequency gain, noise and dynamic range. Therefore, we develop a generic model for integrated Microwave Photonics systems. The key element of the processor is the reconfigurable optical core. It requires high flexibility and versatility to enable reconfigurable interconnections between subsystems as well as the synthesis of photonic integrated circuits. For this element, we focus on a 2-dimensional photonic waveguide mesh based on the interconnection of tunable couplers. Within the framework of this Thesis, we have proposed two novel interconnection schemes, aiming for a mesh design with a high level of versatility. Focusing on the hexagonal waveguide mesh, we explore the synthesis of a high variety of photonic integrated circuits and particular Microwave Photonics applications that can potentially be performed on a single hardware. In addition, we report the first-ever demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate a world-record number of functionalities on a single photonic integrated circuit enabling over 30 different functionalities from the 100 that could be potentially obtained with a simple seven hexagonal cell structure. The resulting device can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks as well as quantum information systems. Our work is an important step towards this paradigm and sets the base for a new era of generic-purpose photonic integrated systems.Los dispositivos integrados de fotónica de microondas ofrecen soluciones optimizadas para los sistemas de información y comunicación. Generalmente, están compuestos por diferentes arquitecturas en las que subsistemas ópticos y electrónicos se integran para optimizar las prestaciones, el consumo, el tamaño y el coste del dispositivo final. Hasta ahora, los circuitos/chips de propósito específico se han diseñado para proporcionar una funcionalidad concreta, requiriendo así un número considerable de iteraciones entre las etapas de diseño, fabricación y medida, que origina tiempos de desarrollo largos y costes demasiado elevados. Una alternativa, inspirada por las FPGA (del inglés Field Programmable Gate Array), es el procesador fotónico programable. Este dispositivo combina la integración de subsistemas de microondas, ópticos y electrónicos para realizar, mediante la programación de los mismos y sus interconexiones, diferentes funcionalidades. En este trabajo, proponemos por primera vez el concepto del procesador de propósito general, así como su arquitectura. Además, con el fin de diseñar, optimizar y evaluar las prestaciones básicas del dispositivo, hemos desarrollado un modelo analítico extremo a extremo basado en las componentes del campo electromagnético. El modelo desarrollado proporciona como resultado la ganancia, el ruido y el rango dinámico global para distintas configuraciones de modulación y detección, en función de los subsistemas y su configuración. El elemento principal del procesador es su núcleo óptico reconfigurable. Éste requiere un alto grado de flexibilidad y versatilidad para reconfigurar las interconexiones entre los distintos subsistemas y para sintetizar los circuitos para el procesado óptico. Para este subsistema, proponemos el diseño de guías de onda reconfigurables para la creación de mallados bidimensionales. En el marco de esta tesis, hemos propuesto dos nuevos nodos de interconexión óptica para mallas reconfigurables, con el objetivo de obtener un mayor grado de versatilidad. Una vez escogida la malla hexagonal para el núcleo del procesador, hemos analizado la configuración de un gran número de circuitos fotónicos integrados y de funcionalidades de fotónica de microondas. El trabajo se ha completado con la demonstración de la primera malla reconfigurable integrada en un chip de silicio, demostrando además la síntesis de 30 de las 100 funcionalidades que potencialmente se pueden obtener con la malla diseñada compuesta de 7 celdas hexagonales. Este hecho supone un record frente a los sistemas de propósito específico. El sistema puede aplicarse en diferentes campos como las comunicaciones, los sensores químicos y biomédicos, el procesado de señales, la gestión y procesamiento de redes y los sistemas de información cuánticos. El conjunto del trabajo realizado representa un paso importante en la evolución de este paradigma, y sienta las bases para una nueva era de dispositivos fotónicos de propósito general.Els dispositius integrats de Fotònica de Microones oferixen solucions optimitzades per als sistemes d'informació i comunicació. Generalment, estan compostos per diferents arquitectures en què subsistemes òptics i electrònics s'integren per a optimitzar les prestacions, el consum, la grandària i el cost del dispositiu final. Fins ara, els circuits/xips de propòsit específic s'han dissenyat per a proporcionar una funcionalitat concreta, requerint així un nombre considerable d'iteracions entre les etapes de disseny, fabricació i mesura, que origina temps de desenrotllament llargs i costos massa elevats. Una alternativa, inspirada per les FPGA (de l'anglés Field Programmable Gate Array), és el processador fotònic programable. Este dispositiu combina la integració de subsistemes de microones, òptics i electrònics per a realitzar, per mitjà de la programació dels mateixos i les seues interconnexions, diferents funcionalitats. En este treball proposem per primera vegada el concepte del processador de propòsit general, així com la seua arquitectura. A més, a fi de dissenyar, optimitzar i avaluar les prestacions bàsiques del dispositiu, hem desenrotllat un model analític extrem a extrem basat en els components del camp electromagnètic. El model desenrotllat proporciona com resultat el guany, el soroll i el rang dinàmic global per a distintes configuracions de modulació i detecció, en funció dels subsistemes i la seua configuració. L'element principal del processador és el seu nucli òptic reconfigurable. Este requerix un alt grau de flexibilitat i versatilitat per a reconfigurar les interconnexions entre els distints subsistemes i per a sintetitzar els circuits per al processat òptic. Per a este subsistema, proposem el disseny de guies d'onda reconfigurables per a la creació de mallats bidimensionals. En el marc d'esta tesi, hem proposat dos nous nodes d'interconnexió òptica per a malles reconfigurables, amb l'objectiu d'obtindre un major grau de versatilitat. Una vegada triada la malla hexagonal per al nucli del processador, hem analitzat la configuració d'un gran nombre de circuits fotónicos integrats i de funcionalitats de fotónica de microones. El treball s'ha completat amb la demostració de la primera malla reconfigurable integrada en un xip de silici, demostrant a més la síntesi de 30 de les 100 funcionalitats que potencialment es poden obtindre amb la malla dissenyada composta de 7 cèl·lules hexagonals. Este fet suposa un rècord enfront dels sistemes de propòsit específic. El sistema pot aplicarse en diferents camps com les comunicacions, els sensors químics i biomèdics, el processat de senyals, la gestió i processament de xarxes i els sistemes d'informació quàntics. El conjunt del treball realitzat representa un pas important en l'evolució d'este paradigma, i assenta les bases per a una nova era de dispositius fotónicos de propòsit general.Pérez López, D. (2017). Integrated Microwave Photonic Processors using Waveguide Mesh Cores [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/91232TESI