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Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.
Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15âmm2 of area. Four tested microchips were measured to consume only 113âpW with a resolution of 0.21â°C and an inaccuracy of ±1.65â°C, which represents a 628Ă reduction in power compared to prior-art without a significant reduction in performance
Capacitive Microaccelerometers And Fabrication Methods
Disclosed are moveable microstructures comprising in-plane capacitive microaccelerometers, with submicro-gravity resolution (17 pF/g). Themicrostructures are fabricated in thick(> 100 ”m) siliconon-insulator (SOI) substrates or silicon substrates using a two-mask fully-dry release process that provides large seismic mass (> 10 milli-g), reduced capacitive gaps, and reduced in-plane stiffness. Fabricated devices may be interfaced to a high resolution switched-capacitor CMOS IC that eliminates the need for area-consuming reference capacitors. The measured sensitivity is 83 mV/mg (17 pF/g) and the output noise floor is -91 dBm/Hz at 10 Hz (corresponding to an acceleration resolution of 170 ng/âHz). The IC consumes 6 mW power and measures 0.65 mm2 core area.Georgia Tech Research Corporatio
A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS
This paper presents a CMOS current comparator which employs nonlinear feedback to obtain high-accuracy (down to 1.5 pA) and high-speed for low input currents (8 ns@50 nA). This structure is much faster for low currents (below 10 /spl mu/A) than other previous nonlinear feedback comparators. Particularly, when compared to the fastest current comparator reported up to now, the new one operates at more that 100 times faster for a 1 nA current, with smaller area occupation and similar power consumption. In addition, the new comparator is virtually insensitive to mismatch and capable of operating with supply voltages as low as 1 V
Noise and thermal stability of vibrating micro-gyrometers preamplifiers
The preamplifier is a critical component of gyrometer's electronics. Indeed
the resolution of the sensor is limited by its signal to noise ratio, and the
gyrometer's thermal stability is limited by its gain drift. In this paper, five
different kinds of preamplifiers are presented and compared. Finally, the
design of an integrated preamplifier is shown in order to increase the gain
stability while reducing its noise and size.Comment: Submitted on behalf of EDA Publishing Association
(http://irevues.inist.fr/EDA-Publishing
High-Resolution ADCs Design in Image Sensors
This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-iïŹcations such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) in ultra-low power and high-resolution analog-to-digital converters (ADCs) including successive approximation register (SAR) for biomedical imaging application. The results show that with broad range of mismatch error, the SFDR is enhanced by about 10 dB with the proposed performance enhancement technique, which makes it suitable for high resolution image sensors sensing systems
Capacitor Mismatch Calibration Technique to Improve the SFDR of 14-Bit SAR ADC
This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC
A handheld high-sensitivity micro-NMR CMOS platform with B-field stabilization for multi-type biological/chemical assays
We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: 14 x 6 x 11 cmÂł, weight: 1.4 kg), the system is capable to detect<100 pM of Enterococcus faecalis derived DNA from a 2.5 ÎŒL sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in 0.18 ÎŒm CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT â 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption (120x), hardware volume (175x), and weight (96x)
Configurable 3D-integrated focal-plane sensor-processor array architecture
A mixed-signal Cellular Visual Microprocessor architecture with digital processors is
described. An ASIC implementation is also demonstrated. The architecture is composed of a
regular sensor readout circuit array, prepared for 3D face-to-face type integration, and one or
several cascaded array of mainly identical (SIMD) processing elements. The individual array
elements derived from the same general HDL description and could be of different in size, aspect
ratio, and computing resources
A CMOS Analog Front-End for Tunnelling Magnetoresistive Spintronic Sensing Systems
This paper presents a CMOS readout circuit for
an integrated and highly-sensitive tunnel-magnetoresistive
(TMR) sensor. Based on the characterization of the TMR sensor
in the finite-element simulation, using COMSOL Multiphysics,
the circuit including a Wheatstone bridge and an analogue
front-end (AFE) circuit, were designed to achieve low-noise and
low-power sensing. We present a transimpedance amplifier
(TIA) that biases and amplifies a TMR sensor array using
switched-capacitors external noise filtering and allows the
integration of TMR sensors on CMOS without decreasing the
measurement resolution. Designed using TSMC 0.18 ÎŒm 1V
technology, the amplifier consumes 160 nA at 1.8 V supply to
achieve a dc gain of 118 dB and a bandwidth of 3.8 MHz. The
results confirm that the full system is able to detect the magnetic
field in the pico-Tesla range with low circuit noise
(2.297 pA/âHz) and low power consumption (86 ÎŒW). A
concurrent reduction in the power consumption and attenuation
of noise in TMR sensors makes them suitable for long-term
deployment in spintronic sensing systems
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