Entwurf und Analyse von Integrierten CMOS Hochspannungs-Treibern in Niederspannungs-Technologien

With scaling technology, the nominal I/O voltage of standard transistors has been reduced from 5.0 V in 0.25-um processes to 2.5 V in 65-nm. However, the supply voltages of some applications cannot be reduced at the same rate as that of shrinking technologies. Since high-voltage (HV-) compatible transistors are not available for some recent technologies and need time to be designed after developing a new process technology, designing HV-circuits based on stacked transistors has better benefits because such circuits offer technology independence and full integration with digital circuits to provide system on-chip solutions. However, the HV-circuits, especially HV-drivers, which are used for switching circuits, have a low efficiency because of the high on-resistance resulted by the stacked transistors. Therefore, the main goal of this work is to design HV-drivers with a minimum on- resistance. To achieve this goal, initially, the gate voltage of each N-stacked transistor is calculated for driving the maximum current in the pull-up and pull-down paths of the HV-driver for various supply voltages. This calculation is performed using the computer algebra system MAXIMA. Regarding the results, which are presented in mathematical formulae, a circuit design methodology is presented to design a circuit to provide the required gate voltage of the each stacked nMOS or pMOS transistor of an HV-driver. Based on this design methodology, a 2-stacked and a 3-stacked CMOS HV-driver is designed in 65-nm TSMC with I/O standard transistors with a nominal voltage of 2.5 V. The simulation results show that the provided gate voltages track approximately the ideal values. In comparison to prior work, the pull-up on-resistances of these HV-drivers are improved about 36% for the maximum allowed supply voltages of 5.0 V and 7.5 V and the pull-down on-resistances have an improvement of 40% and 46%, respectively. For switching a buck converter, the designed 3-stacked CMOS HV-driver is optimised by increasing the number of transistors in each stack. The circuit defined as 3HVDv1 with an area of about 0.187 mm2 is implemented and fabricated on chips using two different package technologies: chip-in-package and chip-on-board. The parasitic effects of bond wires and packaging are discussed in detail. In addition to this main goal, 3- and a 4-stacked CMOS HV-drivers, 3HVDv2 and 4HVDv3, are designed in view of the drawbacks identified during the design, implementation, simulations and measurements; however, the second design (4HVDv3) is an improved form of the first one (3HVDv2). This HV-driver, 4HVDv3, has improved benefits compared to the other designed circuits and also the common HV-drivers, because it can be applied for supply voltages ranging from 3.5 V to 7.5 V. This range is extended by 66%; no reference voltages are required since the regulating of the stacked main transistors is achieved by using a self-biasing cascade method.Mit der Skalierung der CMOS-Technologie wurde die Nominal-Spannung der I/O Transistoren von 5,0 V in 0,25-um Prozess auf 2,5 V in 65-nm reduziert. Es kann jedoch nicht die Versorgungsspannung von einigen Anwendungen mit derselben Rate verringert werden. Daher werden hochspannungskompatible Transistoren für die Schaltungsentwicklung eingesetzt, aber diese speziellen Komponenten sind noch nicht für die neuentwickelten Technologien verfügbar und werden erst in einiger Zeit einsatzbereit sein. Daher ist die Kaskadierung von einzelnen Standard MOS-Transistoren vorteilhaft, da nicht nur eine erhöhte Spannungsfestigkeit erreicht wird, sondern diese Methode Technologie- Unabhängigkeit bietet und volle Integration mit digitalen Schaltungen, System-On-Chip, ermöglicht. Jedoch haben die Hochspannungs- (HV-) Schaltungen basierend auf dieser Methode, wie Treiber, die Abwärtswandler umschalten, einen niedrigen Wirkungsgrad aufgrund des hohen On-Widerstandes durch die gestapelten Transistoren. Das Ziel dieser Arbeit ist, einen HV-Treiber mit einem minimalen On-Widerstand zu entwickeln. Um das zu erreichen, wird zuerst die Gate-Spannung jedes gestapelten Transistors zum Antreiben mit dem maximalen Strom im Pull-up und Pull-down-Pfad des HV-Treibers für verschiedene Versorgungsspannungen berechnet. Diese Berechnung wird mit Hilfe des Computer-Algebra-Systems MAXIMA durchgeführt. Im Hinblick auf die Ergebnisse, die in mathematischen Formeln erfolgen, wird eine Methodologie für Schaltungsentwürfe dargestellt, um die erforderten Gate-Spannungen zu generieren. Auf Basis dieser Design-Methodik, wird ein 2- und ein 3-fach gestapelter CMOS HV-Treiber in 65-nm-TSMC Technologie mit I/O-Standard-Transistoren mit einer Nennspannung von 2,5 V entworfen. Die Simulationsergebnisse zeigen, dass die generierten Gate-Spannungen in etwa den Idealwerten entsprechen. Für die maximal zulässigen Versorgungsspannungen von 5,0 V und 7,5 V, sind die Pull-up On-Widerstände der entwickelten HV-Treiber etwa 36% und die Pull-down On-Widerstände 40% und 46% im Vergleich zu einer früher veröffentlichten Arbeit verbessert. Für die Umschaltung eines Abwärtswandlers wird der entworfene 3-fach gestapelte CMOS HV-Treiber durch Erhöhung der Transistoren-Anzahl in jedem Stapel optimiert, und als 3HVDv1 definiert. Die Schaltung hat eine Fläche von etwa 0.187 mm² und ist auf Chips implementiert. Zwei verschiedene Gehäusetechnologien (Chip-in-Package und Chip-on-Board) wurden gefertigt. Neben diesem Hauptziel, verbesserte 3- und 4-fach gestapelte CMOS HV-Treiber, 3HVDv2 und 4HVDv3, zu entwerfen; ist jedoch der zweite Treiber eine verbesserte Form des ersten und kann für Versorgungsspannungen im Bereich von 3,5 V bis 7,5 V, der eine Erweiterung von 66% im Vergleich zu üblichen Treiber aufweist, angewendet werden. Aufgrund des Selbstvorspannungs-Verfahren, werden die Haupttransistoren des Treibers ohne zusätzliche Referenzspannung für die aktive Pull-Down und Pull-Up Zustände reguliert

유전알고리즘 및 강화학습을 사용한 고속 회로 설계 자동화 프레임워크

학위논문(석사) -- 서울대학교대학원 : 융합과학기술대학원 지능정보융합학과, 2022.2. 전동석.Although design automation is a key enabler of modern large-scale digital systems, automating the transistor-level circuit design process still remains a challenge. Some recent works suggest that deep learning algorithms could be adopted to find optimal transistor dimensions in relatively small circuitry such as analog amplifiers. However, those approaches are not capable of exploring different circuit structures to meet the given design constraints. In this work, we propose an automatic circuit design framework that can generate practical circuit structures from scratch as well as optimize the size of each transistor, considering performance and reliability. We employ the framework to design level shifter circuits, and the experimental results show that the framework produces novel level shifter circuit topologies and the automatically optimized designs achieve 2.8-5.3× lower PDP than prior arts designed by human experts.설계 자동화는 대규모 디지털 시스템을 가능하게 하는 핵심 요소이지만 트랜지스터 수준에서 회로 설계 프로세스를 자동화하는 것은 여전히 어려운 과제로 남아 있습니다. 최근 연구에서는 아날로그 앰프와 같은 비교적 작은 회로에서 최적의 성능을 보이는 트랜지스터 크기를 찾기 위해 deep learning 알고리즘을 활용할 수 있다고 말합니다. 그러나 이러한 접근 방식은 주어진 설계 constraint를 충족하는 다른 회로 구조 탐색에 적용하기 어렵습니다. 본 연구에서는 성능과 신뢰성을 고려하여 각 트랜지스터의 크기를 최적화할 뿐만 아니라 처음부터 실용적인 회로 구조를 생성할 수 있는 자동 회로 설계 framework를 제안합니다. 우리는 framework를 사용하여 level shifter 회로를 설계했으며 실험 결과는 프레임워크가 새로운 level shifter 회로 토폴로지를 생성하고 자동으로 최적화된 설계가 인간 전문가가 설계한 선행 기술보다 2.8-5.3배 더 낮은 PDP를 달성한다는 것을 보여줍니다.Abstract i Contents ii List of Tables iv List of Figures v List of Algorithms vi 1 Introduction 1 2 Related work 6 2.1 Genetic Algorithm 6 2.2 NeuroEvolution of Augmenting Topologies (NEAT) 7 2.3 Reinforcement Learning (RL) 10 2.4 DDPG, D4PG, and PPO 12 2.5 Level Shifter 14 3 Proposed circuit design framework 17 3.1 Topology Generator 17 3.2 Circuit Optimizer 25 4 Experiment Result 32 4.1 Level Shifter Design 32 4.2 Topology Generation 34 4.3 Circuit Optimization 36 4.4 Test Chip Fabrication 42 4.5 Applicability of Topology Generator 47 5 Conclusion 50 Abstract (In Korean) 57석

A Charge-Recycling Scheme and Ultra Low Voltage Self-Startup Charge Pump for Highly Energy Efficient Mixed Signal Systems-On-A-Chip

The advent of battery operated sensor-based electronic systems has provided a pressing need to design energy-efficient, ultra-low power integrated circuits as a means to improve the battery lifetime. This dissertation describes a scheme to lower the power requirement of a digital circuit through the use of charge-recycling and dynamic supply-voltage scaling techniques. The novel charge-recycling scheme proposed in this research demonstrates the feasibility of operating digital circuits using the charge scavenged from the leakage and dynamic load currents inherent to digital design. The proposed scheme efficiently gathers the “ground-bound” charge into storage capacitor banks. This reclaimed charge is then subsequently recycled to power the source digital circuit. The charge-recycling methodology has been implemented on a 12-bit Gray-code counter operating at frequencies of less than 50 MHz. The circuit has been designed in a 90-nm process and measurement results reveal more than 41% reduction in the average energy consumption of the counter. The total energy savings including the power consumed for the generation of control signals aggregates to an average of 23%. The proposed methodology can be applied to an existing digital path without any design change to the circuit but with only small loss to the performance. Potential applications of this scheme are described, specifically in wide-temperature dynamic power reduction and as a source for energy harvesters. The second part of this dissertation deals with the design and development of a self-starting, ultra-low voltage, switched-capacitor (SC) DC-DC converter that is essential to an energy harvesting system. The proposed charge-pump based SC-converter operates from 125-mV input and thus enables battery-less operation in ultra-low voltage energy harvesters. The charge pump does not require any external components or expensive post-fabrication processing to enable low-voltage operation. This design has been implemented in a 130-nm CMOS process. While the proposed charge pump provides significant efficiency enhancement in energy harvesters, it can also be incorporated within charge recycling systems to facilitate adaptable charge-recycling levels. In total, this dissertation provides key components needed for highly energy-efficient mixed signal systems-on-a-chip

Digital and analog TFET circuits: Design and benchmark

In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10 nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDDlower than 0.4 V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions