Design and fabrication of suspended-gate MOSFETs for MEMS resonator, switch and memory applications

Wireless communication systems and handset devices are showing a rapid growth in consumer and military applications. Applications using wireless communication standards such as personal connectivity devices (Bluetooth), mobile systems (GSM, UMTS, WCDMA) and wireless sensor network are the opportunities and challenges for the semi-conductor industry. The trend towards size and weight reduction, low power consumption and increased functionalities induces major technological issues. Today, the wireless circuit size is limited by the use of lots of external or "off-chip" components. Among them, quartz crystal, used as the time reference in any wireless systems, is the bottleneck of the miniaturization. Microelectromechanical systems (MEMS) is an emerging technology which has the capability of replacing the quartz. Based on similar technology than the Integrated Circuit (IC), MEMS are referred as electrostatically, thermally or piezoelectrically actuated mechanical structures. In this thesis, a new MEMS device based on the hybridization of a mechanical vibrating structure and a solid-sate MOS transistor has been developed. The Resonant Suspended-Gate MOSFET (RSG-MOSFET) device combines both advantages of a high mechanical quality factor and the transistor intrinsic gain. The physical mechanisms behind the actuation and the behavior of this device were deeply investigated and a quasi-static model was developed and validated, based on measured characteristics. Furthermore, the dynamic model of the RSG-MOSFET was created, taking into account the non-linear mechanical vibrations of the gate and the EKV model, used for MOSFET modeling. Two fabrication processes were successfully developed to demonstrate the proof of concept of such a device and to optimize the performances respectively. Aluminum-silicon (Al-Si1%) and pure silicon-based RSG-MOSFETs were successfully fabricated. DC and AC characterizations on both devices enabled to understand, extract and evaluate the mechanical and MOSFET effects. A specifically developed RF characterization methodology was used to measure the linear and non-linear behaviors of the resonator and to evaluate the influence of each polarization voltages on the signal response. RSG-MOSFET with resonant frequencies ranging from 5MHz to 90MHz and quality factor up to 1200 were measured. Since MEMS resonator quality factor is strongly degraded by air damping, a 0-level thin film vacuum packaging (10-7 mBar) process was developed, compatible with both AlSi-based and silicon-based RSG-MOSFET. The technology has the unique advantage of being done on already released structure and the room temperature process makes it suitable for above-IC integration. In parallel, a front-end compatible process was defined and major build blocks were developed in industrial environment at STMicroelectronics. This technology is based on the Silicon-On-Nothing technology, originally developed for advanced transistor, and therefore making the MEMS resonator process compatible with CMOS co-integration. DC characterizations of SG-MOSFET had shown interesting performances of this device for current switch and memory applications. Mechanical contact of the gate with the MOSFET channel induces a current switching slope greater than 0.8mV/decade, much better than the theoretical MOSFET limit of 60mV/decade. Maximum switch isolations of -37dB at 2 GHz and -27dB at 10GHz were measured on these devices. A novel MEMS-memory has been demonstrated, based on the direct charge injection to the storage media by the mechanical contact of the metal gate. Charge injection and retention mechanisms were investigated based on measured devices. Cycling study of up to 105 cycles were performed without noticing major degradations of the electrical behavior neither mechanical fatigue of the suspended gate. The measured retention time places this memory in between the DRAM and the FLASH memories. A scaling study has shown integration and compatibilities capabilities with existing CMOS

Front-end circuits for chemical and molecular sensing

This research demonstrates two building blocks for CMOS integrated sensor IC for molecular or chemical sensing. One of them for molecular sensing is the capacitance sensing circuit to detect the change of the dielectric constant of novel nanowell devices. The size of nanowell (10nm-100nm) enables high fidelity detection and analysis through Broadband Dielectric Spectroscopy (BDS) of the parallel-plate capacitor formed by the nanowell and the targeted molecules. The signal tranduction is done by a novel, continuous-time detection circuit using a low-noise lock-in architecture which generates the current output containing the information about the admittance of the sensor as a function of the frequency for BDS. This current signal is processed in the current domain by a low power current-mode A/D converter. The current signal transducer has a quasilinear capacitance resolution of 164pA/aF (at 1Ghz) and power consumption of only 30uW in 0.18um TSMC CMOS technology. Another building block is a low noise front end for feature extraction for gas and nanoparticle detection using Van der Waals sensors. The output of such a sensor consists of particle specific information in the low frequency range from 0 to 100 KHz in the form of stochastic fluctuations. Such detection schemes are termed as fluctuation enhanced sensing, which exploit the statistics of the noise in the low frequency spectrum. The front end consists of a low pass filter bank to process the amplified signal from a low-noise transimpedance amplifier. It handles the noise-like information signal from the sensor with filters having increasing cut-off frequencies. It is designed to operate at temperature as high as 200C with low leakage currents to maximize the stochastic fluctuation noise generation. The front-end system was fabricated with TSMC 0.18um technology and tested. The gain of the front-end circuit is at least 87dB and its power consumption with one transimpedance amplifier and 10 filters is just 1.1mW. Moreover, the worst-case maximum input current signal is 0.2uApp while satisfying 5% THD and the equivalent input current noise level is under 7nA. The front-end circuit demonstrates the considerably high dynamic range with the low noise input range suitable for applications for sensing using fluctuation enhanced techniques

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Some Studies on Si-nanotube Based FETs

Silicon-nano-tube (SiNT) MOSFETs have been analyzed recently in order to investigate their suitability for future ultra-large scale integration (ULSI) applications. Based on the study so for, it could be safely stated that the SiNT MOSFETs are very promising for future ULSI asthey could be scaled down to 22nm gate length and below effectively. The SiNT MOSFET provides ultimate electrostatic controllability to the gates in order to counter the short-channel effects because of its hollow cylindrical shape. In SiNT MOSFETs, two gates, an outer gate and an inner gate, can act independently or together in order to realize the multi-threshold voltage transistors characteristics or high drain current, respectively. The SiNT MOSFET is particularly considered to be unique in the sense that, unlike other MG MOS structures, it provides excellent SCE immunity even when the diameter of the tube is increased as long as the channel thickness is kept same. Subthreshold electrical characteristics of SiNT FET have been studied through device simulation and it has been confirmed that the device outperforms GAA and other MG devices completely. However, in the best of our knowledge, neither analog nor RF performance of the device has been studied till date in order to access its potential in system-on-chip applications. Therefore, we have analyzed the analog as well as the RF characteristics of SiNT FETs using the ATLAS, a 3D device simulator from SILVACO. Besides, the characteristics of SiNT MOSFETs have also been compared with the same of a nanowire based GAA FET to quantify the improvement in the performance. In this work, Si-nanotube MOSFETs (SiNT FET) with catalytic metal gates are proposed for gas sensing applications. P-channel SiNT FET with palladium (Pd) metal gate is proposed for hydrogen sensing , whereas N-channel SiNT FET with silver (Ag) metal gate can be used for\ oxygen gas sensing. A simulation based study has been carried out using ATLAS-3D numerical simulator, and it is found that SiNT FETs have more efficiency towards the iii hydrogen and oxygen detection than the recently proposed cylindrical gate-all-around (GAA) MOSFETs. Further, effect of variation of the channel length (Lg) and channel thickness (tSi) on the gas sensing sensitivity of the sensors are also studied. In the presented work, an analysis into the performance of a Dual Material Gate Single Dielectric Si-nanotube Tunnel FET has been done. Numerous simulations were done to determine the influence of work functions of both the gate materials on the electrical characteristics of the device. Comparative study was done between Dual Material Gate device and Single Material Gate device. Parameters like intrinsic capacitances as well as transconducatnce were also determined. The same analytic approach was extended to Dual Material Gate Hetero Dielectric Sinanotube Tunnel FET to analyze the improved performance of the device compared to itsSingle Dielectric Dua Material Gate counterpart .Thus the work presented had all together analyzed attributes of ncorporating Dual Material Gate as well as Hetero Dielectric in Sinanotube Tunnel FET structures. Extensive simulations for the presented work were performed by using two dimensional device simulator (ATLASTM SILVACO Int.

III-V Nanowire MOSFET High-Frequency Technology Platform

This thesis addresses the main challenges in using III-V nanowireMOSFETs for high-frequency applications by building a III-Vvertical nanowire MOSFET technology library. The initial devicelayout is designed, based on the assessment of the current III-V verticalnanowire MOSFET with state-of-the-art performance. The layout providesan option to scale device dimensions for the purpose of designing varioushigh-frequency circuits. The nanowire MOSFET device is described using1D transport theory, and modeled with a compact virtual source model.Device assessment is performed at high frequencies, where sidewall spaceroverlaps have been identified and mitigated in subsequent design iterations.In the final stage of the design, the device is simulated with fT > 500 GHz,and fmax > 700 GHz.Alongside the III-V vertical nanowire device technology platform, adedicated and adopted RF and mm-wave back-end-of-line (BEOL) hasbeen developed. Investigation into the transmission line parameters revealsa line attenuation of 0.5 dB/mm at 50 GHz, corresponding to state-ofthe-art values in many mm-wave integrated circuit technologies. Severalkey passive components have been characterized and modeled. The deviceinterface module - an interconnect via stack, is one of the prominentcomponents. Additionally, the approach is used to integrate ferroelectricMOS capacitors, in a unique setting where their ferroelectric behavior iscaptured at RF and mm-wave frequencies.Finally, circuits have been designed. A proof-of-concept circuit, designedand fabricated with III-V lateral nanowire MOSFETs and mm-wave BEOL, validates the accuracy of the BEOL models, and the circuit design. Thedevice scaling is shown to be reflected into circuit performance, in aunique device characterization through an amplifier noise-matched inputstage. Furthermore, vertical-nanowire-MOSFET-based circuits have beendesigned with passive feedback components that resonate with the devicegate-drain capacitance. The concept enables for device unilateralizationand gain boosting. The designed low-noise amplifiers have matching pointsindependent on the MOSFET gate length, based on capacitance balancebetween the intrinsic and extrinsic capacitance contributions, in a verticalgeometry. The proposed technology platform offers flexibility in device andcircuit design and provides novel III-V vertical nanowire MOSFET devicesand circuits as a viable option to future wireless communication systems

Modeling and Characterization of 4H-SIC MOSFETs: High Field, High Temperature, and Transient Effects

We present detailed physics based numerical models for characterizing 4H-Silicon Carbide lateral MOSFETs and vertical power DMOSFETs for high temperature, high field, DC, AC and transient switching operating conditions. A complete 2-D Drift-Diffusion based device simulator has been developed specifically for SiC MOSFETs, to evaluate device performance in a variety of operating scenarios, and to extract relevant physical parameters. We have developed and implemented room and high temperature mobility models for bulk phonon and impurity scattering, surface phonon scattering, Coulomb scattering from interface traps, and surface roughness scattering. High temperature models for interface trap density of states and occupation probability of interface traps are also implemented. By rigorous comparison of simulated I-V characteristics to experimental data at high temperatures, physical parameters like interface trap density of states, surface step height, saturation velocity, etc. have been extracted. Insight into relative importance of scattering mechanisms influencing transport in SiC MOSFETs has been provided. We show that the strongest contribution to low current in SiC MOSFETs is from the loss of mobile inversion charge due to large amount of trapping at the interface, and due to very low surface mobility arising due to a rough SiC-SiO2 interface. We show that surface roughness scattering dominates at high gate biases and is the most important scattering mechanism in 4H-SiC MOSFETs. Switching characteristics of SiC lateral MOSFETs have been modeled and simulated using our custom device simulator. A comprehensive generation-recombination model for interaction between inversion layer electrons and interface traps has been developed. Using this model, we have modeled the time-dependent occupation of interface traps spread inside the SiC bandgap. We have measured the transient characteristics of these devices, and compare our simulation to experiment and have extracted capture cross-sections of interface traps. Using the coupled experiment and modeling approach, we are able to distinguish between fast interface traps and slow oxide traps, and explain how they contribute to threshold voltage instability. High power 4H-SiC DMOSFET operation in the ON and the OFF states has also been analyzed. We show that in current generation SiC DMOSFETs, the ON resistance is dominated by the channel resistance instead of the drift-layer resistance. This makes the design of SiC DMOSFETs far from ideal. OFF state blocking capability and breakdown due to impact ionization of the DMOSFETs are also modeled and simulated. We show that the 4H-SiC DMOSFETs have excellent leakage characteristics and can support extremely high OFF state drain voltages

Implantable active high resolution electrodes for real-time field potential mapping. Elettrodi attivi impiantabili ad alta risoluzione per mappatura in tempo reale del potenziale di campo

In this work a novel device for neural field potential measurement and mapping is presented, analysed and tested. The design layout and strutture of the C-100-A active semiconductor implantable needles are presented. The devices are thoroughly simulated and characterized, and possible issues and critical points are spotted. Solution strategies are developed and first in-vivo measurement results are finally presente