Characterization and Emulation of Low-Voltage Power Line Channels for Narrowband and Broadband Communication

The demand for smart grid and smart home applications has raised the recent interest in power line communication (PLC) technologies, and has driven a broad set of deep surveys in low-voltage (LV) power line channels. This book proposes a set of novel approaches, to characterize and to emulate LV power line channels in the frequency range from0.15to 10 MHz, which closes gaps between the traditional narrowband (up to 500 kHz) and broadband (above1.8 MHz) ranges

Characterization and Emulation of Low-Voltage Power Line Channels for Narrowband and Broadband Communication

The demand for smart grid and smart home applications has raised the recent interest in power line communication (PLC) technologies, and has driven a broad set of deep surveys in low-voltage (LV) power line channels. This book proposes a set of novel approaches, to characterize and to emulate LV power line channels in the frequency range from0.15to 10 MHz, which closes gaps between the traditional narrowband (up to 500 kHz) and broadband (above1.8 MHz) ranges

Classification and modeling of power line noise using machine learning techniques

A thesis submitted in ful lment of the requirements for the degree of Doctor of Philosophy in the School of Electrical and Information Engineering Faculty of Engineering and Built Environment June 2017The realization of robust, reliable and e cient data transmission have been the theme of recent research, most importantly in real channel such as the noisy, fading prone power line communication (PLC) channel. The focus is to exploit old techniques or create new techniques capable of improving the transmission reliability and also increasing the transmission capacity of the real communication channels. Multi-carrier modulation scheme such as Orthogonal Frequency Division Multiplexing (OFDM) utilizing conventional single-carrier modulation is developed to facilitate a robust data transmission, increasing transmission capacity (e cient bandwidth usage) and further reducing design complexity in PLC systems. On the contrary, the reliability of data transmission is subjected to several inhibiting factors as a result of the varying nature of the PLC channel. These inhibiting factors include noise, perturbation and disturbances. Contrary to the Additive White Gaussian noise (AWGN) model often assumed in several communication systems, this noise model fails to capture the attributes of noise encountered on the PLC channel. This is because periodic noise or random noise pulses injected by power electronic appliances on the network is a deviation from the AWGN. The nature of the noise is categorized as non-white non-Gaussian and unstable due to its impulsive attributes, thus, it is labeled as Non-additive White Gaussian Noise (NAWGN). These noise and disturbances results into long burst errors that corrupts signals being transmitted, thus, the PLC is labeled as a horrible or burst error channel. The e cient and optimal performance of a conventional linear receiver in the white Gaussian noise environment can therefore be made to drastically degrade in this NAWGN environment. Therefore, transmission reliability in such environment can be greatly enhanced if we know and exploit the knowledge of the channel's statistical attributes, thus, the need for developing statistical channel model based on empirical data. In this thesis, attention is focused on developing a recon gurable software de ned un-coded single-carrier and multicarrier PLC transceiver as a tool for realizing an optimized channel model for the narrowband PLC (NB-PLC) channel. First, a novel recon gurable software de ned un-coded single-carrier and multi-carrier PLC transceiver is developed for real-time NB-PLC transmission. The transceivers can be adapted to implement di erent waveforms for several real-time scenarios and performance evaluation. Due to the varying noise parameters obtained from country to country as a result of the dependence of noise impairment on mains voltages, topology of power line, place and time, the developed transceivers is capable of facilitating constant measurement campaigns to capture these varying noise parameters before statistical and mathematically inclined channel models are derived. Furthermore, the single-carrier (Binary Phase Shift Keying (BPSK), Di erential BPSK (DBPSK), Quadrature Phase Shift Keying (QPSK) and Di erential QPSK (DQPSK)) PLC transceiver system developed is used to facilitate a First-Order semi-hidden Fritchman Markov modeling (SHFMM) of the NB-PLC channel utilizing the e cient iterative Baum- Welch algorithm (BWA) for parameter estimation. The performance of each modulation scheme is evaluated in a mildly and heavily disturbed scenarios for both residential and laboratory site considered. The First-Order estimated error statistics of the realized First- Order SHFMM have been analytically validated in terms of performance metrics such as: log-likelihood ratio (LLR), error-free run distribution (EFRD), error probabilities, mean square error (MSE) and Chi-square ( 2) test. The reliability of the model results is also con rmed by an excellent match between the empirically obtained error sequence and the SHFMM regenerated error sequence as shown by the error-free run distribution plot. This thesis also reports a novel development of a low cost, low complexity Frequency-shift keying (FSK) - On-o keying (OOK) in-house hybrid PLC and VLC system. The functionality of this hybrid PLC-VLC transceiver system was ascertained at both residential and laboratory site at three di erent times of the day: morning, afternoon and evening. A First and Second-Order SHFMM of the hybrid system is realized. The error statistics of the realized First and Second-Order SHFMMs have been analytically validated in terms of LLR, EFRD, error probabilities, MSE and Chi-square ( 2). The Second-Order SHFMMs have also been analytically validated to be superior to the First-Order SHFMMs although at the expense of added computational complexity. The reliability of both First and Second-Order SHFMM results is con rmed by an excellent match between the empirical error sequences and SHFMM re-generated error sequences as shown by the EFRD plot. In addition, the multi-carrier (QPSK-OFDM, Di erential QPSK (DQPSK)-OFDM) and Di erential 8-PSK (D8PSK)-OFDM) PLC transceiver system developed is used to facilitate a First and Second-Order modeling of the NB-PLC system using the SHFMM and BWA for parameter estimation. The performance of each OFDM modulation scheme in evaluated and compared taking into consideration the mildly and heavily disturbed noise scenarios for the two measurement sites considered. The estimated error statistics of the realized SHFMMs have been analytically validated in terms of LLR, EFRD, error probabilities, MSE and Chi-square ( 2) test. The estimated Second-Order SHFMMs have been analytically validated to be outperform the First-Order SHFMMs although with added computational complexity. The reliability of the models is con rmed by an excellent match between the empirical data and SHFMM generated data as shown by the EFRD plot. The statistical models obtained using Baum-Welch to adjust the parameters of the adopted SHFMM are often locally maximized. To solve this problem, a novel Metropolis-Hastings algorithm, a Bayesian inference approach based on Markov Chain Monte Carlo (MCMC) is developed to optimize the parameters of the adopted SHFMM. The algorithm is used to optimize the model results obtained from the single-carrier and multi-carrier PLC systems as well as that of the hybrid PLC-VLC system. Consequently, as deduced from the results, the models obtained utilizing the novel Metropolis-Hastings algorithm are more precise, near optimal model with parameter sets that are closer to the global maxima. Generally, the model results obtained in this thesis are relevant in enhancing transmission reliability on the PLC channel through the use of the models to improve the adopted modulation schemes, create adaptive modulation techniques, develop and evaluate forward error correction (FEC) codes such as a concatenation of Reed-Solomon and Permutation codes and other robust codes suitable for exploiting and mitigating noise impairments encountered on the low voltage NB-PLC channel. Furthermore, the recon gurable software de ned NB-PLC transceiver test-bed developed can be utilized for future measurement campaign as well as adapted for multiple-input and multiple-output (MIMO) PLC applications.MT201

Characterization and Emulation of Low-Voltage Power Line Channels for Narrowband and Broadband Communication

This thesis proposes a set of novel approaches to characterize and to emulate LV power line channels in the frequency range from 0.15 to 10MHz, which close gaps between the traditional narrowband (up to 500 kHz) and broadband (above 1.8MHz) ranges

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re[CA] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor IRodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967TESI