Electrostatic Discharge For Sysyem On Chip Applications

Integrated Circuit (IC) component level Electrostatic Discharge (ESD) requisites have stayed constant essentially for past two decades, having said so since the silicon technologies showing rapid advanced and efficacious control methods have prodigiously amended as well as improved. ESD standard JEDEC requirements has been part of success criteria on determine the ESD stress level in semiconductor industry. The standards applied across all product where its specification define for ESD test method, procedure, evaluation and classifying Human Body Model (HBM) a ESD model sensitive on component and ESD sensitivity to charge namely Charged Device Model (CDM). Apparently, the main gaps for this industrial standard missing of defining the withstand ESD stress voltage and recommended step test. Nevertheless, there is room of improvement to recommend guideline for when performing preliminary setup on pin combination for HBM test. In this thesis, will recommend a model change to more authentic but safe ESD stress target levels predicated on actual field data accumulated from 14nm and 22nm differences technology process devices as part of data for the learning on estimation the accuracy of the standards JEDEC JS001 and JS002 requirements on HBM and CDM respectively. Nonetheless, a much effective and time saving way established for data analysis of measurement leakage current increase before and after ESD test using JMP statistics tool on 14nm and 22nm small package devices. Driving to the standardization the new guideline for HBM successfully established. Lastly, the result of this research demonstrates the actual CDM test collected data on 14nm and 22nm more accurate on predicting the withstand voltage compare the peak current methodology

Design guidelines for assessing and controlling spacecraft charging effects

The need for uniform criteria, or guidelines, to be used in all phases of spacecraft design is discussed. Guidelines were developed for the control of absolute and differential charging of spacecraft surfaces by the lower energy space charged particle environment. Interior charging due to higher energy particles is not considered. A guide to good design practices for assessing and controlling charging effects is presented. Uniform design practices for all space vehicles are outlined

System efficient ESD design concept for soft failures

This research covers the topic of developing a systematic methodology of studying electrostatic discharge (ESD)-induced soft failures. ESD-induced soft failures (SF) are non-destructive disruptions of the functionality of an electronic system. The soft failure robustness of a USB3 Gen 1 interface is investigated, modeled, and improved. The injection is performed directly using transmission line pulser (TLP) with varying: pulse width, amplitude, polarity. Characterization provides data for failure thresholds and a SPICE circuit model that describes the transient voltage and current at the victim. Using the injected current, the likelihood of a SF is predicted. ESD protection by transient voltage suppressor (TVS) diodes is numerically simulated in several configurations. The results strongly suggest the viability of using well-established hard failure mitigation techniques for improving SF robustness, and the possibility of using numerical simulation for optimization purposes. A concept of soft failure system efficient ESD design (SF-SEED) is proposed and shown to be effective --Abstract, page iv

Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Characterization and modeling of ESD events, risk and protection

“The ESD (Electrostatic discharge) failures have been raising critical reliability problems in electronic devices design. However, not all the ESD scenarios have been specified by the IEC standard and the characterizations of the ESD risk for different scenarios are essential to evaluate the ESD robustness of the devices in the real word. The insulation of plastic enclosures provides protection against ESD to the electronic system inside. However, seams between plastic parts are often unavoidable. Different plastic arrangements are constructed to investigate the spark length and current derivatives and to understand the ESD spark behavior for geometries having spark lengths longer than the values predicted by Paschen’s law. For the wearable devices, the core difference between the posture assumed for IEC 61000-4-2 human metal discharge and a discharge to a wearable device is the impedance between the charged body and the grounded structure discharged to. The results show that the current measured in the brush-by scenario can reach values twice as high as the current specified in the IEC standard. A simulation model using the measured impedance and Rompe and Weizel’s law provides predictions on the peak current derivative when the spark length is varied. The increasing peak current derivative with shorter spark length indicates stronger field coupling to the devices. SEED(System-efficient ESD design) modeling helps the designer to predict the ESD risk at the early stage, an accurate TVS model can be used to study the transient response of the external TVS and the on-chip protection when applied in a typical high-speed input/output (I/O) interface”--Abstract, page iv

Trick or Heat? Manipulating Critical Temperature-Based Control Systems Using Rectification Attacks

Temperature sensing and control systems are widely used in the closed-loop control of critical processes such as maintaining the thermal stability of patients, or in alarm systems for detecting temperature-related hazards. However, the security of these systems has yet to be completely explored, leaving potential attack surfaces that can be exploited to take control over critical systems. In this paper we investigate the reliability of temperature-based control systems from a security and safety perspective. We show how unexpected consequences and safety risks can be induced by physical-level attacks on analog temperature sensing components. For instance, we demonstrate that an adversary could remotely manipulate the temperature sensor measurements of an infant incubator to cause potential safety issues, without tampering with the victim system or triggering automatic temperature alarms. This attack exploits the unintended rectification effect that can be induced in operational and instrumentation amplifiers to control the sensor output, tricking the internal control loop of the victim system to heat up or cool down. Furthermore, we show how the exploit of this hardware-level vulnerability could affect different classes of analog sensors that share similar signal conditioning processes. Our experimental results indicate that conventional defenses commonly deployed in these systems are not sufficient to mitigate the threat, so we propose a prototype design of a low-cost anomaly detector for critical applications to ensure the integrity of temperature sensor signals.Comment: Accepted at the ACM Conference on Computer and Communications Security (CCS), 201

Effect of Electrostatic Discharge on Electrical Characteristics of Discrete Electronic Components

This article reports on preliminary results of a study conducted to examine how temporary electrical overstress seed fault conditions in discrete power electronic components that cannot be detected with reliability tests but impact longevity of the device. These defects do not result in formal parametric failures per datasheet specifications, but result in substantial change in the electrical characteristics when compared with pristine device parameters. Tests were carried out on commercially available 600V IGBT devices using transmission line pulse (TLP) and system level ESD stress. It was hypothesized that the ESD causes local damage during the ESD discharge which may greatly accelerate degradation mechanisms and thus reduce the life of the components. This hypothesis was explored in simulation studies where different types of damage were imposed to different parts of the device. Experimental results agree qualitatively with the simulation for a number of tests which will motivate more in-depth modeling of the damage

On-Chip ESD Protection Design: Optimized Clamps

The extensive use of Integrated Circuits (ICs) means complex working conditions for these tiny chips. To guarantee the ICs could work properly in various environments, some special protection strategies are required to improve the reliability of system. From all the possible reliability issues, the electrostatics discharge (ESD) might be the most common one. The peak current of electrostatics can be as high as tens of amperes and the peak voltage can be over thousand voltages. In contrast, the size of semiconductor device fabricated is continuing to scale down, making it even more vulnerable to high level overstress and current surge induced by ESD event. To protect the on-chip semiconductor from damage, some extra clamp cells are put together to consist a network. The network can redirect the superfluous current through the ESD network and clamp the voltage to a low level. In this dissertation, one design concept is introduced that uses the combination of some basic ESD devices to meet different requirements first, and then tries to establish parasitic current path among these devices to further increase the current handling capability. Some design cases are addressed to demonstrate this design concept is valid and efficient: 1. A combination of silicon-controlled-rectifier (SCR) and diode cluster is implemented to resolve the overshoot issue under fast ESD event. 2. A new SCR structure is introduced, which can be used as padding device to increase the clamping voltage without affecting other parameters. Based on this padding device, two design cases are introduced. 3. A controllable SCR clamp structure is presented, which has high current handling capability and can be controlled with by small signal. All these structures and topologies described in this dissertation are compatible with most of popular semiconductor fabrication process