Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Thin-film piezoelectric-on-substrate resonators and narrowband filters

A new class of micromachined devices called thin-film piezoelectric-on-substrate (TPoS) resonators is introduced, and the performance of these devices in RF and sensor applications is studied. TPoS resonators benefit from high electromechanical coupling of piezoelectric transduction mechanism and superior acoustic properties of a substrate such as single crystal silicon. Therefore, the motional impedance of these resonators are significantly smaller compared to typical capacitively-transduced counterparts while they exhibit relatively high quality factor and power handling and can be operated in air. The combination of all these features suggests TPoS resonators as a viable alternative for current acoustic devices. In this thesis, design and fabrication methods to realize dispersed-frequency lateral-extensional TPoS resonators are discussed. TPoS devices are fabricated on both silicon-on-insulator and thin-film nanocrystalline diamond substrates. The performance of these resonators in simple and low-power oscillators is measured and compared. Furthermore, a unique coupling technique for implementation of high frequency filters is introduced in which dual resonance modes of a single resonant structure are coupled. The measured results of this work show that these filters are suitable candidates for single-chip implementation of multiple-frequency narrow-band filters with high out-of-band rejection in a small footprint.Ph.D.Committee Chair: Farrokh Ayazi; Committee Member: James D. Meindl; Committee Member: John D. Cressler; Committee Member: Nazanin Bassiri-Gharb; Committee Member: Oliver Bran

Low-Power Energy Efficient Circuit Techniques for Small IoT Systems

Although the improvement in circuit speed has been limited in recent years, there has been increased focus on the internet of things (IoT) as technology scaling has decreased circuit size, power usage and cost. This trend has led to the development of many small sensor systems with affordable costs and diverse functions, offering people convenient connection with and control over their surroundings. This dissertation discusses the major challenges and their solutions in realizing small IoT systems, focusing on non-digital blocks, such as power converters and analog sensing blocks, which have difficulty in following the traditional scaling trends of digital circuits. To accommodate the limited energy storage and harvesting capacity of small IoT systems, this dissertation presents an energy harvester and voltage regulators with low quiescent power and good efficiency in ultra-low power ranges. Switched-capacitor-based converters with wide-range energy-efficient voltage-controlled oscillators assisted by power-efficient self-oscillating voltage doublers and new cascaded converter topologies for more conversion ratio configurability achieve efficient power conversion down to several nanowatts. To further improve the power efficiency of these systems, analog circuits essential to most wireless IoT systems are also discussed and improved. A capacitance-to-digital sensor interface and a clocked comparator design are improved by their digital-like implementation and operation in phase and frequency domain. Thanks to the removal of large passive elements and complex analog blocks, both designs achieve excellent area reduction while maintaining state-of-art energy efficiencies. Finally, a technique for removing dynamic voltage and temperature variations is presented as smaller circuits in advanced technologies are more vulnerable to these variations. A 2-D simultaneous feedback control using an on-chip oven control locks the supply voltage and temperature of a small on-chip domain and protects circuits in this locked domain from external voltage and temperature changes, demonstrating 0.0066 V/V and 0.013 °C/°C sensitivities to external changes. Simple digital implementation of the sensors and most parts of the control loops allows robust operation within wide voltage and temperature ranges.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/138743/1/wanyeong_1.pd

Design of a MEMS-based 52 MHz oscillator

Mechanical resonators are widely applied in time-keeping and frequency reference applications. Mechanical resonators are preferred over electrical resonators because of their high Q. In the $4.1 billion (2008) timing market, quartz crystals are still ubiquitous in electronic equipment. Quartz crystals show excellent performance in terms of stability (shortterm and long-term), power handling, and temperature drift. MEMS resonators are investigated as a potential alternative to the bulky quartz crystals, which cannot be integrated with IC technology. MEMS offer advantages in terms of size, cost price, and system integration. Efforts over recent years have shown that MEMS resonators are able to meet the high performance standards set by quartz. Critical success factors are high Q-factor, low temperature drift, low phase noise, and low power. This PhD thesis addresses the feasibility of scaling MEMS resonators/oscillators to frequencies above 10 MHz. The main deliverable is a 52 MHz MEMS-based oscillator. The MEMS resonators at NXP are processed on 8-inch silicon-on-insulator (SOI) wafers, with a SOI layer thickness of 1.5 µm and a buried oxide layer thickness of 1 µm. The strategic choice for thin SOI substrates has been made for two reasons. First, MEMS processing in thin silicon layers can be done with standard CMOS processing tools. The silicon dioxide layer serves as a sacrificial layer. Second, identical substrates are used for the Advanced Bipolar CMOS DMOS (ABCD) IC-processes. This class of processes can handle high voltages (ABCD2 up to 120V). The high voltage capability is suitable for the transduction of the mechanical resonator. Both MEMS and IC are processed on a similar substrate, since the strategic aim is to integrate the MEMS structure with the IC-process in the long run. Frequency scaling is investigated for both the capacitive and the piezoresistive MEMS resonator. MEMS resonators have been successfully tested from 13 MHz to over 400 MHz. This is achieved by decreasing the size of the resonator with a factor 32. We show that the thin SOI layer and the decreasing size of the resonator increase the effective impedance of the capacitive resonator at higher frequencies. For the piezoresistive resonator, we show that this readout principle is insensitive to geometrical scaling and layer thickness. Therefore, the piezoresistive readout is preferred at high frequencies. The effective impedance can be kept low, at the expense of higher power consumption. Frequency accuracy can be improved by decreasing the initial frequency spread and the temperature drift of the MEMS resonator. The main source of initial frequency spread is geometrical offset, due to the non-perfect pattern transfer from mask layout to SOI. A FEM tool has been developed in Comsol Multiphysics to obtain compensated layouts. The resonance frequency of these designs is first-order compensated for geometric offset. The FEM tool is used to obtain compensated resonators of various designs. We show empirically that the compensation by design is effective on a 52 MHz square plate design. For the compensated design, frequency spread measurements over a complete wafer show that there are other systematic sources of frequency spread. The resonance frequency of the silicon MEMS resonator drifts about –30 ppm/K. This is due to the Young’s modulus of silicon that depends on temperature. We have investigated two compensation methods. The first is passive compensation by coating the silicon resonator with a silicon dioxide skin. The Young’s modulus of silicon dioxide has a positive temperature drift. Measurements on globally oxidized structures show that the right oxide thickness reduces the linear temperature drift of the resonator to zero. A second method uses an oven-control principle. The temperature of the resonator is fixed, independent of the ambient temperature. A demo of this principle has been designed with a piezoresistive resonator in which the dc readout current through the resonator is used to control the temperature of the resonator. With both concepts, more than a factor 10 reduction in temperature drift is achieved. To demonstrate the feasibility of high-frequency oscillators, a MEMS-based 56 MHz oscillator has been designed for which a piezoresistive dogbone resonator is used. The amplifier has been designed in the ABCD2 IC-process. The MEMS oscillator consumes 6.1 mW and exhibits a phase noise of –102 dBc/Hz at 1 kHz offset from the carrier and a floor of –113 dBc/Hz. This demonstrates feasibility of the piezoresistive MEMS oscillator for lowpower, low-noise applications. Summarizing, this PhD thesis work as part of the MEMSXO project at NXP demonstrates a MEMS oscillator concept based on the piezoresistive resonator in thin SOI. It shows that by compensated designs for geometric offset and oven-control to reduce temperature drift, a frequency accuracy can be achieved that can compete with the performance of crystal oscillators. In a benchmark with MEMS competitors the concept shows the lowest phase noise, making it the most suited concept for wireless applications

Interface Circuits for Microsensor Integrated Systems

ca. 200 words; this text will present the book in all promotional forms (e.g. flyers). Please describe the book in straightforward and consumer-friendly terms. [Recent advances in sensing technologies, especially those for Microsensor Integrated Systems, have led to several new commercial applications. Among these, low voltage and low power circuit architectures have gained growing attention, being suitable for portable long battery life devices. The aim is to improve the performances of actual interface circuits and systems, both in terms of voltage mode and current mode, in order to overcome the potential problems due to technology scaling and different technology integrations. Related problems, especially those concerning parasitics, lead to a severe interface design attention, especially concerning the analog front-end and novel and smart architecture must be explored and tested, both at simulation and prototype level. Moreover, the growing demand for autonomous systems gets even harder the interface design due to the need of energy-aware cost-effective circuit interfaces integrating, where possible, energy harvesting solutions. The objective of this Special Issue is to explore the potential solutions to overcome actual limitations in sensor interface circuits and systems, especially those for low voltage and low power Microsensor Integrated Systems. The present Special Issue aims to present and highlight the advances and the latest novel and emergent results on this topic, showing best practices, implementations and applications. The Guest Editors invite to submit original research contributions dealing with sensor interfacing related to this specific topic. Additionally, application oriented and review papers are encouraged.

Digital CMOS ISFET architectures and algorithmic methods for point-of-care diagnostics

Over the past decade, the surge of infectious diseases outbreaks across the globe is redefining how healthcare is provided and delivered to patients, with a clear trend towards distributed diagnosis at the Point-of-Care (PoC). In this context, Ion-Sensitive Field Effect Transistors (ISFETs) fabricated on standard CMOS technology have emerged as a promising solution to achieve a precise, deliverable and inexpensive platform that could be deployed worldwide to provide a rapid diagnosis of infectious diseases. This thesis presents advancements for the future of ISFET-based PoC diagnostic platforms, proposing and implementing a set of hardware and software methodologies to overcome its main challenges and enhance its sensing capabilities. The first part of this thesis focuses on novel hardware architectures that enable direct integration with computational capabilities while providing pixel programmability and adaptability required to overcome pressing challenges on ISFET-based PoC platforms. This section explores oscillator-based ISFET architectures, a set of sensing front-ends that encodes the chemical information on the duty cycle of a PWM signal. Two initial architectures are proposed and fabricated in AMS 0.35um, confirming multiple degrees of programmability and potential for multi-sensing. One of these architectures is optimised to create a dual-sensing pixel capable of sensing both temperature and chemical information on the same spatial point while modulating this information simultaneously on a single waveform. This dual-sensing capability, verified in silico using TSMC 0.18um process, is vital for DNA-based diagnosis where protocols such as LAMP or PCR require precise thermal control. The COVID-19 pandemic highlighted the need for a deliverable diagnosis that perform nucleic acid amplification tests at the PoC, requiring minimal footprint by integrating sensing and computational capabilities. In response to this challenge, a paradigm shift is proposed, advocating for integrating all elements of the portable diagnostic platform under a single piece of silicon, realising a ``Diagnosis-on-a-Chip". This approach is enabled by a novel Digital ISFET Pixel that integrates both ADC and memory with sensing elements on each pixel, enhancing its parallelism. Furthermore, this architecture removes the need for external instrumentation or memories and facilitates its integration with computational capabilities on-chip, such as the proposed ARM Cortex M3 system. These computational capabilities need to be complemented with software methods that enable sensing enhancement and new applications using ISFET arrays. The second part of this thesis is devoted to these methods. Leveraging the programmability capabilities available on oscillator-based architectures, various digital signal processing algorithms are implemented to overcome the most urgent ISFET non-idealities, such as trapped charge, drift and chemical noise. These methods enable fast trapped charge cancellation and enhanced dynamic range through real-time drift compensation, achieving over 36 hours of continuous monitoring without pixel saturation. Furthermore, the recent development of data-driven models and software methods open a wide range of opportunities for ISFET sensing and beyond. In the last section of this thesis, two examples of these opportunities are explored: the optimisation of image compression algorithms on chemical images generated by an ultra-high frame-rate ISFET array; and a proposed paradigm shift on surface Electromyography (sEMG) signals, moving from data-harvesting to information-focused sensing. These examples represent an initial step forward on a journey towards a new generation of miniaturised, precise and efficient sensors for PoC diagnostics.Open Acces

Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance