981 research outputs found

    Analysis of Class-DE PA Using MOSFET Devices With Non-Equally Grading Coefficient

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    Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

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    In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

    Integrated Very High Frequency Switch Mode Power Supplies: Design Considerations

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    Experimental research on the electric vacuum gyro Final technical report

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    Electronic circuitry for suspending electric vacuum gyro rotor in center of electrode spher

    Ultra Wideband 5 W Hybrid Power Amplifier Design Using Silicon Carbide MESFETs

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    Aufgrund des hohen Bandabstandes von SiC besitzen SiC-MESFETs ein hohe Duruchbruchspannung und können folglich bei hohen Versorgungsspannungen betrieben werden. Darüber hinaus besitzen sie eine hohe Elektronensätigungsgeschwindigkeit und Wärmeleitfähigkeit. Aufgrund diese eigenschaften eignen sich diese bauelemente hervorragend für die Entwiklung von breitbandigen Leistungsverstärkern bis in den unteren GHz-Bereich. In dieser Arbeit wird ein neues empirisches Modell für SiC MESFET vorgeschlagen. Ein kommerziell erhältlicher, gehäuster MESFET Typ (CREE CRF24010) wird für die Entwicklung des Modelles verwendet. Messungen wurden sowohl in Arbeitspunkten mit als auch ohne Vorspannung durchgeführt um die Gleichungen und Parameter abzuleiten. Die Cold FET Technik wurde verwendet um die parasitären extrinsischen Elemente zu bestimmen, während die arbeitspunktabhängigen Elemente des Modelles analytisch bei mehreren Arbeitspunkten bestimmt wurden. Nichtlineare Gleichungen für die arbeitspunktabhängigen Elemente wurden ebenfalls abgeleitet. Das so entwickelte Modell für den SiC MESFET wurde sowohl hinsichtlich des Kleinsignal als auch des Großsignalverhaltens überprüft. Fünf verschiedene Generationen von Breitband-Leistungsverstärkern wurden auf Grundlage des entwickelten Modelles implementiert. Dabei wurde keinerlei Impedanztransformator eingesetzt. Eine neuartige breitbandige Biasstruktur wurde entwickelt, um gute Isolation und geringe Verluste über die angestrebte Bandbreite zu erreichen. Die Anpassungsnetzwerke an Eingang, Ausgang und zwischen den Stufen sowie die Parallel-Rückkopplung wurden mit Hilfe von Mikrostreifenleitungstechnik realisiert um die Bandbreite zu erhöhen und die Stabilität zu verbessern. Als erste Generation wird ein einstufiger 5 Watt Leistungsverstärker mit einem SiC MESFET entworfen und aufgebaut, der den Frequenzbereich von 10 MHz bis 2,4 GHz abdeckt. Eine Leistungsverstärkung von 6 dB, 37 dBm Ausgangsleistung, 33% PAE und 52 dBm OIP3 wurden erreicht. Ein zweistufiger Leistungsverstärker mit hoher Verstärkung für die selbe Bandbreite, der einen GaAs und einen SiC MESFET in Kaskade verwendet, wurde ebenfalls aufgebaut. Typische Werte von 23 dB Leistungsverstärkung, 37 dBm Ausgangsleistung, 28 % PAE und 47 dBm OIP3 wurden erreicht. Der Einfluss der Treiberstufe auf die Leistungs- und Linearitätseigenschaften der zweiten Generation wurde untersucht. Basierend auf SiC Chips wurden die dritte und vierte Generation in Form von einstufigen und zweistufigen ultra-breitband Leistungsverstärkern implementiert, die das Frequenzband von 1 MHz bis 5 GHz abdecken. Der Einfluss des GaAs FET Treibers in der vierten Kategorie auf die Gesamteigenschaften wurde ebenfalls diskutiert. Unter Einsatz der Rückkopplungs-Kompensationstechnik wurde ein schmalbandiger 10 W Leistungsverstärkerentwurf mit hoher Verstärkung, basierend auf einem SiC Chip, als fünftes Beispiel vorgestellt. Alle Leistungs- und Linearitäts-Ergebnisse wurden über das gesamte Frequenzband ermittelt. Die Entwurfsprozedur wird detailliert beschrieben und die Ergebnisse werden diskutiert und ausführlich mit den Simulationen verglichen.SiC MESFETs have an enormous potential for realizing high-power amplifiers at microwave frequencies due to their wide band-gap features of high breakdown field, high electron saturation velocity and high operating temperature. In this thesis, a new empirical model for SiC MESFET is proposed. A commercially packaged high power MESFET device (CREE CRF24010) is adopted for the model development. Both hot and cold bias condition measurements are performed to derive equations and parameters. Cold FET technique is used to extract the parasitic extrinsic elements whereas the bias-dependent model elements are extracted analytically from multiple bias points. Nonlinear equations for the bias dependent elements are derived, too. The derived model for the SiC MESFET has been verified in small signal as well as large signal performances. Five different generations of broadband power amplifiers based on the developed model have been implemented. No impedance transformer was used at all. A novel broadband choke structure has been developed to obtain good isolation and low loss over the desired bandwidth. Input, interstage and output matching networks and shunt feedback topology have been designed based on microstip technique to increase the bandwidth and improve the stability. In the first generation, a single stage 5-watt power amplifier using a SiC MESFET covering the frequency range from 10 MHz to 2.4 GHz is designed and fabricated. A power gain of 6 dB, 37 dBm output power, 33 % PAE and 52 dBm OIP3 have been achieved. A high gain two stage power amplifier covering the same bandwidth using a GaAs- and a SiC- MESFET in cascade also has been fabricated. Typical values of 23 dB power gain, 37 dBm output power, 28 % PAE and 47 dBm OIP3 have been obtained. The impact of the driver stage on power and linearity performances of the second generation has been discussed. Based on SiC Chip, the third and the fourth generation represent ultra wideband single stage and two stage power amplifiers, covering the frequency band from 1 MHz to 5 GHz have been simulated. Small signal and harmonic balance simulations based on ADS have been introduced. The impact of the GaAs FET driver in the fourth category on the overall performances also has been discussed. Using feedback compensation technique, a 10-W narrow band high gain power amplifier design based on SiC Chip has been presented as a fifth example. All power and linearity results were obtained over the whole frequency band. The design procedure is given in detail and the results are being discussed and compared with simulations extensively

    Space-Compliant Design of a Millimeter-Wave GaN-on-Si Stacked Power Amplifier Cell through Electro-Magnetic and Thermal Simulations

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    The stacked power amplifier is a widely adopted solution in CMOS technology to overcome breakdown limits. Its application to compound semiconductor technology is instead rather limited especially at very high frequency, where device parasitic reactances make the design extremely challenging, and in gallium nitride technology, which already offers high breakdown voltages. Indeed, the stacked topology can also be advantageous in such scenarios as it can enhance gain and chip compactness. Moreover, the higher supply voltages and lower supply currents beneficially impact on reliability, thus making the stacked configuration an attractive solution for space applications. This paper details the design of two stacked cells, differing in their inter-stage matching strategy, conceived for space applications at Ka-band in 100 nm GaN-on-Si technology. In particular, the design challenges related to the thermal constraints posed by space reliability and to the electro-magnetic cross-talk issues that may arise at millimeter-wave frequencies are discussed. The best cell achieves at saturation, in simulation, 3 W of output power at 36 GHz with associated gain and efficiency in excess of 7 dB and 35%, respectively

    Millimeter-Wave Concurrent Dual-Band Sige Bicmos Rfic Phased-Array Transmitter and Components

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    A concurrent dual-band phased-array transmitter (TX) and its constituent components are studied in this dissertation. The TX and components are designed for the unlicensed bands, 22–29 and 57–64 GHz, using a 0.18-μm BiCMOS technology. Various studies have been done to design the components, which are suitable for the concurrent dual-band phased-array TX. The designed and developed components in this study are an attenuator, switch, phase shifter, power amplifier and power divider. Attenuators play a key role in tailoring main beam and side-lobe patterns in a phased-array TX. To perform the function in the concurrent dual-band phased-array TX, a 22–29 and 57–64 GHz concurrent dual-band attenuator with low phase variations is designed. Signal detection paths are employed at the output of the phased-array TX to monitor the phase and amplitude deviations/errors, which are larger in the high-frequency design. The detected information enables the TX to have an accurate beam tailoring and steering. A 10–67 GHz wide-band attenuator, covering the dual bands, is designed to manipulate the amplitude of the detected signal. New design techniques for an attenuator with a wide attenuation range and improved flatness are proposed. Also, a topology of dual-function circuit, attenuation and switching, is proposed. The switching turns on and off the detection path to minimize the leakages while the path is not used. Switches are used to minimize the number of components in the phased-array transceiver. With the switches, some of the bi-directional components in the transceiver such as an attenuator, phase shifter, filter, and antenna can be shared by the TX and receiver (RX) parts. In this dissertation, a high-isolation switch with a band-pass filtering response is proposed. The band-pass filtering response suppresses the undesired harmonics and intermodulation products of the TX. Phase shifters are used in phased-array TXs to steer the direction of the beam. A 24-GHz phase shifter with low insertion loss variation is designed using a transistor-body-floating technique for our phased-array TX. The low insertion loss variation minimizes the interference in the amplitude control operation (by attenuator or variable gain amplifier) in phased-array systems. BJTs in a BiCMOS process are characterized across dc to 67 GHz. A novel characterization technique, using on-wafer calibration and EM-based de-embedding both, is proposed and its accuracy at high frequencies is verified. The characterized BJT is used in designing the amplifiers in the phased-array TX. A concurrent dual-band power amplifier (PA) centered at 24 and 60 GHz is proposed and designed for the dual-band phased-array TX. Since the PA is operating in the dual frequency bands simultaneously, significant linearity issues occur. To resolve the problems, a study to find significant intermodulation (IM) products, which increase the third intermodulation (IM3) products most, has been done. Also, an advanced simulation and measurement methodology using three fundamental tones is proposed. An 8-way power divider with dual-band frequency response of 22–29 and 57–64 GHz is designed as a constituent component of the phased-array TX
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