Continuous-time cascaded ΣΔ modulators for VDSL: A comparative study

This paper describes new cascaded continuous-time ΣΔ modulators intended to cope with very high-rate digital subscriber line specifications, i.e 12-bit resolution within a 20-MHz signal bandwidth. These modulators have been synthesized using a new methodology that is based on the direct synthesis of the whole cascaded architecture in the continuous-time domain instead of using a discrete-to-continuous time transformation as has been done in previous approaches. This method allows to place the zeroes/poles of the loop-filter transfer function in an optimal way and to reduce the number of analog components, namely, transconductors and/or amplifiers, resistors, capacitors and digital-to-analog converters. This leads to more efficient topologies in terms of circuitry complexity, power consumption and robustness with respect to circuit non-idealities. A comparison study of the synthesized architectures is done considering their sensitivity to most critical circuit error mechanisms. Time-domain behavioral simulations are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

A design tool for high-resolution high-frequency cascade continuous- time Σ∆ modulators

Event: Microtechnologies for the New Millennium, 2007, Maspalomas, Gran Canaria, SpainThis paper introduces a CAD methodology to assist the de signer in the implementation of continuous-time (CT) cas- cade Σ∆ modulators. The salient features of this methodology ar e: (a) flexible behavioral modeling for optimum accuracy- efficiency trade-offs at different stages of the top-down synthesis process; (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity; a nd (c) mixed knowledge-based and optimization-based architec- tural exploration and specification transmission for enhanced circuit performance. The applicability of this methodology will be illustrated via the design of a 12 bit 20 MHz CT Σ∆ modulator in a 1.2V 130nm CMOS technology.Ministerio de Ciencia y Educación TEC2004-01752/MICMinisterio de Industria, Turismo y Comercio FIT-330100-2006-134 SPIRIT Projec

Micromachined vibratory gyroscopes controlled by a high order band-pass sigma delta modulator.

Abstract—This work reports on the design of novel closed-loop control systems for the sense mode of a vibratory-rate gyroscope based on a high-order sigma-delta modulator (SDM). A low-pass and two distinctive bandpass topologies are derived, and their advantages discussed. So far, most closed-loop force-feedback control systems for these sensors were based on low-pass SDM’s. Usually, the sensing element of a vibratory gyroscope is designed with a high quality factor to increase the sensitivity and, hence, can be treated as a mechanical resonator. Furthermore, the output characteristic of vibratory rate gyroscopes is narrowband amplitude- modulated signal. Therefore, a bandpass M is a more appropriate control strategy for a vibratory gyroscope than a low-pass SDM. Using a high-order bandpass SDM, the control system can adopt a much lower sampling frequency compared with a low-pass SDM while achieving a similar noise floor for a given oversampling ratio (OSR). In addition, a control system based on a high-order bandpass SDM is superior as it not only greatly shapes the quantization noise, but also alleviates tonal behavior, as is often seen in low-order SDM control systems, and has good immunities to fabrication tolerances and parameter mismatch. These properties are investigated in this study at system level

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

Implicit feed-forward compensated op-amp with split pairs

Disclosed are systems implementing an implicit Feed-Forward Compensated (FFC) op-amp, where the main FFC port is realized by the P-side of the CMOS input structure of the 2nd and 3rd stages of the op-amp, while the main signal path is through the N-side. According to some embodiments, to balance the relative strengths of the main path and feed-forward paths, the 2nd-stage NMOS input pair is split into two pairs, one is used to route the main path while the other is used for auxiliary FFC. The disclosed implicit FCC op-amp is unconditionally stable with adequate phase lead. According to some embodiments, the disclosed op-amp, which may be a wide-band op-amp, can be used in highly linear applications operative at intermediate frequency (IF), such as signal buffers for high-performance data converters or radio-frequency (RF) modulators and demodulators, continuous-time (CT) filters or sigma-delta data converters.Board of Regents, University of Texas Syste