Emerging Design Methodology And Its Implementation Through Rns And Qca

Digital logic technology has been changing dramatically from integrated circuits, to a Very Large Scale Integrated circuits (VLSI) and to a nanotechnology logic circuits. Research focused on increasing the speed and reducing the size of the circuit design. Residue Number System (RNS) architecture has ability to support high speed concurrent arithmetic applications. To reduce the size, Quantum-Dot Cellular Automata (QCA) has become one of the new nanotechnology research field and has received a lot of attention within the engineering community due to its small size and ultralow power. In the last decade, residue number system has received increased attention due to its ability to support high speed concurrent arithmetic applications such as Fast Fourier Transform (FFT), image processing and digital filters utilizing the efficiencies of RNS arithmetic in addition and multiplication. In spite of its effectiveness, RNS has remained more an academic challenge and has very little impact in practical applications due to the complexity involved in the conversion process, magnitude comparison, overflow detection, sign detection, parity detection, scaling and division. The advancements in very large scale integration technology and demand for parallelism computation have enabled researchers to consider RNS as an alternative approach to high speed concurrent arithmetic. Novel parallel - prefix structure binary to residue number system conversion method and RNS novel scaling method are presented in this thesis. Quantum-dot cellular automata has become one of the new nanotechnology research field and has received a lot of attention within engineering community due to its extremely small feature size and ultralow power consumption compared to COMS technology. Novel methodology for generating QCA Boolean circuits from multi-output Boolean circuits is presented. Our methodology takes as its input a Boolean circuit, generates simplified XOR-AND equivalent circuit and output an equivalent majority gate circuits. During the past decade, quantum-dot cellular automata showed the ability to implement both combinational and sequential logic devices. Unlike conventional Boolean AND-OR-NOT based circuits, the fundamental logical device in QCA Boolean networks is majority gate. With combining these QCA gates with NOT gates any combinational or sequential logical device can be constructed from QCA cells. We present an implementation of generalized pipeline cellular array using quantum-dot cellular automata cells. The proposed QCA pipeline array can perform all basic operations such as multiplication, division, squaring and square rooting. The different mode of operations are controlled by a single control line

Quantum-dot Cellular Automata: Review Paper

Quantum-dot Cellular Automata (QCA) is one of the most important discoveries that will be the successful alternative for CMOS technology in the near future. An important feature of this technique, which has attracted the attention of many researchers, is that it is characterized by its low energy consumption, high speed and small size compared with CMOS.  Inverter and majority gate are the basic building blocks for QCA circuits where it can design the most logical circuit using these gates with help of QCA wire. Due to the lack of availability of review papers, this paper will be a destination for many people who are interested in the QCA field and to know how it works and why it had taken lots of attention recentl

Design and performance analysis of a new efficient coplanar quantum-dot cellular automata adder

Quantum-dot cellular automata (QCA) nanotechnology has the potential for revolutionizing the way computers are used. QCA computing has numerous advantages of ultra-low energy dissipation, improved performance and high device density. An adder is the most elementary component in arithmetic units of processors. Lot of work has been in progress to design and implement efficient adder circuits in QCA nanotechnology. This paper presents design and performance analysis of a new efficient coplanar adder in QCA nanotechnology. The proposed adder design uses 20% less QCA cells as compared to previous similar design due to better arrangement of QCA cells in the layout and has a delay of 1 clock cycle with an area of 0.04 µm2. The proposed adder has 19% less average leakage energy dissipation, 28% less average switching energy dissipation, and 25% less average energy dissipation than the best reported previous coplanar adder design. The cost function of proposed efficient adder is equal to best reported previous coplanar adder

Implementation of Binary to Gray Code Converters in Quantum Dot Cellular Automata

Quantum dot cellular automaton (QCA) are dominant nanotechnology which has been used extensively in digital circuits and systems. It is a promising alternative to complementary metal–oxide–semiconductor (CMOS) technology with many enticing features such as high-speed, low power consumption and higher switching frequency than transistor based technology. The code converters are the basic unit for transformation of data to execute arithmetic processes. In this paper, QCA based 2-bit binary-to- gray; 3-bit binary-to-gray and 4-bit binary-to-gray code converter have been proposed. The proposed design reduces the number of cells, area and raises switching speed. The simulations are completed using QCADesigner and Microwindlite tool which is widely used for simulation and verification

Design and analysis of efficient QCA reversible adders

Quantum-dot cellular automata (QCA) as an emerging nanotechnology are envisioned to overcome the scaling and the heat dissipation issues of the current CMOS technology. In a QCA structure, information destruction plays an essential role in the overall heat dissipation, and in turn in the power consumption of the system. Therefore, reversible logic, which significantly controls the information flow of the system, is deemed suitable to achieve ultra-low-power structures. In order to benefit from the opportunities QCA and reversible logic provide, in this paper, we first review and implement prior reversible full-adder art in QCA. We then propose a novel reversible design based on three- and five-input majority gates, and a robust one-layer crossover scheme. The new full-adder significantly advances previous designs in terms of the optimization metrics, namely cell count, area, and delay. The proposed efficient full-adder is then used to design reversible ripple-carry adders (RCAs) with different sizes (i.e., 4, 8, and 16 bits). It is demonstrated that the new RCAs lead to 33% less garbage outputs, which can be essential in terms of lowering power consumption. This along with the achieved improvements in area, complexity, and delay introduces an ultra-efficient reversible QCA adder that can be beneficial in developing future computer arithmetic circuits and architecture